Semiconductor structure having bottom isolation and enhanced carrier mobility

1. A semiconductor structure, comprising:

a first dielectric layer disposed on a semiconductor substrate;

a bottom source/drain region disposed on the first dielectric layer and isolated from the semiconductor substrate by the first dielectric layer;

a second dielectric layer disposed on the bottom source/drain region;

a top source/drain region disposed on the second dielectric layer and isolated from the bottom source/drain region by the second dielectric layer; and

an air gap disposed within the semiconductor substrate and surrounded by the first dielectric layer.

2. The semiconductor structure of claim 1 , wherein the bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy.

3. The semiconductor structure of claim 1 , wherein the air gap is disposed below the bottom source/drain region.

4. The semiconductor structure of claim 1 , wherein the first dielectric layer and the second dielectric layer are formed together as the same dielectric layer.

5. The semiconductor structure of claim 1 , further comprising a nanosheet stack structure comprising a first plurality of layers and a second plurality of layers, wherein the first plurality of layers corresponds to the bottom source/drain region and the second plurality of layers corresponds to the top source/drain region.

6. The semiconductor structure of claim 5 , wherein the nanosheet stack structure comprises a first work function metal disposed around the first plurality of layers and a second work function metal disposed around the second plurality of layers.

7. The semiconductor structure of claim 6 , wherein the first work function metal comprises a material that corresponds to the bottom source/drain region and the second work function metal comprises a material that corresponds to the top source/drain region.

8. The semiconductor structure of claim 6 , wherein the first work function metal is disposed on the second work function metal.

9. A semiconductor structure, comprising:

a first dielectric layer disposed on a semiconductor substrate and encapsulating an air gap in the semiconductor substrate;

a bottom source/drain region disposed on the first dielectric layer above the encapsulated air gap;

a second dielectric layer disposed on the bottom source/drain region; and

a top source/drain region disposed on the second dielectric layer.

10. The semiconductor structure of claim 9 , wherein the bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy.

11. The semiconductor structure of claim 9 , wherein the first dielectric layer and the second dielectric layer are formed together as the same dielectric layer.

12. The semiconductor structure of claim 9 , further comprising a nanosheet stack structure comprising a first plurality of layers and a second plurality of layers, wherein the first plurality of layers corresponds to the bottom source/drain region and the second plurality of layers corresponds to the top source/drain region.

13. The semiconductor structure of claim 12 , wherein the nanosheet stack structure comprises a first work function metal disposed around the first plurality of layers and a second work function metal disposed around the second plurality of layers.

14. The semiconductor structure of claim 13 , wherein the first work function metal comprises a material that corresponds to the bottom source/drain region and the second work function metal comprises a material that corresponds to the top source/drain region.

15. The semiconductor structure of claim 13 , wherein the first work function metal is disposed on the second work function metal.

16. A method for fabricating a semiconductor structure, comprising:

etching a channel between a pair of gate structures down into a semiconductor substrate of the semiconductor structure;

growing a first sacrificial epitaxial layer in the channel;

growing a bottom source/drain region in the channel on the first sacrificial epitaxial layer;

growing a second sacrificial epitaxial layer in the channel on the bottom source/drain region;

growing a top source/drain region in the channel on the second sacrificial epitaxial layer;

removing the first and second sacrificial epitaxial layers, the removal exposing surfaces of the semiconductor substrate, bottom source/drain region and top source/drain region; and

forming a dielectric layer on the exposed surfaces of the semiconductor substrate, bottom source/drain region and top source/drain region.

17. The method of claim 16 , wherein forming the dielectric layer on the exposed surfaces of the semiconductor substrate comprises forming an air gap in the semiconductor structure beneath the bottom source/drain region.

18. The method of claim 16 , wherein:

growing a bottom source/drain region comprises growing the bottom source/drain region with a compressive pFET epitaxy; and

growing a top source/drain region comprises growing the top source/drain region with a tensile nFET epitaxy.

19. The method of claim 16 , wherein forming the dielectric layer on the exposed surfaces of the bottom source/drain region and top source/drain region comprises forming the dielectric layer such that the top source/drain region is isolated from the bottom source/drain region and the bottom source/drain region is isolated from the semiconductor substrate by the dielectric layer.

20. The semiconductor structure of claim 6 , wherein the first work function metal and the second work function metal comprise different materials.