Semiconductor devices with backside power rail and method thereof

1. A semiconductor structure, comprising:

one or more channel layers;

a gate structure engaging the one or more channel layers;

a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure;

a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure;

a second source/drain feature connected to a second side of the one or more channel layers that is opposite to the first side of the one or more channel layers, wherein the gate structure is disposed between the first and the second source/drain features;

a contact plug disposed over and electrically connected to the second source/drain feature;

a second dielectric cap disposed over the contact plug;

a first via disposed under and electrically connected to the first source/drain feature; and

a power rail disposed under and electrically connected to the first via.

2. The semiconductor structure of claim 1 , further comprising:

a silicide feature disposed between the first dielectric cap and the first source/drain feature.

3. The semiconductor structure of claim 1 , further comprising:

a dielectric feature disposed under the second source/drain feature and isolating the second source/drain feature from the power rail.

4. The semiconductor structure of claim 3 , further comprising:

a second via penetrating the second dielectric cap and electrically connected to the contact plug.

5. The semiconductor structure of claim 4 , wherein the first dielectric cap and the second dielectric cap include a same material.

6. The semiconductor structure of claim 4 , wherein the first dielectric cap and the second dielectric cap include different materials.

7. The semiconductor structure of claim 4 , wherein the first dielectric cap includes a material having a lower dielectric constant than that of a material in the second dielectric cap.

8. The semiconductor structure of claim 4 , wherein the first dielectric cap is thicker than the second dielectric cap.

9. The semiconductor structure of claim 1 , further comprising a first interconnect structure over the first dielectric cap, wherein the first dielectric cap isolates the first source/drain feature from the first interconnect structure.

10. A semiconductor structure, comprising:

one or more channel layers;

a gate structure engaging the one or more channel layers;

a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure;

a second source/drain feature connected to a second side of the one or more channel layers and adjacent to the gate structure;

a first dielectric cap disposed over the first source/drain feature;

a contact plug disposed over and electrically connected to the second source/drain feature;

two gate spacers;

two contact etch stop layers, wherein each of the two contact etch stop layers is laterally between the first dielectric cap and each of the two gate spacers;

a first interconnect structure over the first dielectric cap and the contact plug, wherein the first interconnect structure is electrically connected to the contact plug and is isolated from the first source/drain feature by the first dielectric cap;

a first via disposed under and electrically connected to the first source/drain feature; and

a second interconnect structure disposed under and electrically connected to the first via.

11. The semiconductor structure of claim 10 , wherein the first dielectric cap directly contacts a top surface of the first source/drain feature.

12. The semiconductor structure of claim 10 , further comprising a silicide layer between the first dielectric cap and the first source/drain feature.

13. The semiconductor structure of claim 10 , further comprising:

a second via penetrating the second dielectric cap, wherein the first interconnect structure is electrically connected to the contact plug through the second via.

14. The semiconductor structure of claim 10 , further comprising a second dielectric cap disposed above the contact plug and below the first interconnect structure.

15. The semiconductor structure of claim 14 , further comprising a second via penetrating the second dielectric cap, wherein the first interconnect structure is electrically connected to the contact plug through the second via.

16. The semiconductor structure of claim 14 , wherein the first dielectric cap and the second dielectric cap include different dielectric materials.

17. A semiconductor structure, comprising:

one or more channel layers;

a gate structure engaging the one or more channel layers;

a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure;

a second source/drain feature connected to a second side of the one or more channel layers and adjacent to the gate structure;

a first dielectric cap disposed over the first source/drain feature and isolating the first source/drain feature from conductors directly above the first source/drain feature, wherein the first dielectric cap is not disposed over the gate structure;

one or more conductors directly above the second source/drain feature and electrically connected to the second source/drain feature; and

a backside via disposed directly below the first source/drain feature and electrically connected to the first source/drain feature.

18. The semiconductor structure of claim 17 , further comprising:

a backside interconnect structure disposed below and electrically connected to the backside via.

19. The semiconductor structure of claim 17 , further comprising:

a second dielectric cap disposed over the second source/drain feature, wherein one of the one or more conductors goes through the second dielectric cap.

20. The semiconductor structure of claim 19 , where a top surface of the first dielectric cap and a top surface of the second dielectric cap are substantially co-planar.