Semiconductor structure with extended contact structure
Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
1. A semiconductor structure, comprising:
a substrate;
nanostructures formed over the substrate;
a gate structure formed around the nanostructures;
inner spacers sandwiched between the nanostructures;
a spacer formed on a sidewall of the gate structure over the inner spacers,
a source/drain structure adjacent to the inner spacers; and
a contact formed in the source/drain structure and protruding from a top surface of the source/drain structure,
wherein a bottom portion of the spacer is laterally sandwiched between the source/drain structure and the gate structure.
2. The semiconductor structure as claimed in claim 1 , wherein a portion of the gate structure is vertically sandwiched between the spacer and the nanostructures.
3. The semiconductor structure as claimed in claim 1 , further comprising:
a metal silicide layer formed in the source/drain structure,
wherein first portions of the source/drain structure sandwiched between the inner spacers and the metal silicide layer are wider than second portions of the source/drain structure sandwiched between the nanostructures and the metal silicide layer.
4. The semiconductor structure as claimed in claim 3 , wherein a bottom surface of the metal silicide layer is lower than a bottom surface of one of the nanostructures.
5. The semiconductor structure as claimed in claim 1 , wherein the inner spacers have curved sidewalls in direct contact with the source/drain structure.
6. A semiconductor structure, comprising:
a substrate;
nanostructures formed over the substrate;
inner spacers sandwiched between the nanostructures;
a gate structure surrounding the nanostructures;
a source/drain structure attached to the nanostructures, wherein the inner spacers laterally sandwiched between the source/drain structure and the gate structure; and
a contact vertically extending into the source/drain structure such that a portion of the source/drain structure is laterally sandwiched by the contact and the inner spacer,
wherein a bottom surface of the contact is lower than a top surface of a top most one of the nanostructures.
7. The semiconductor structure as claimed in claim 6 , wherein a top surface of the contact is higher than a top surface of the gate structure.
8. The semiconductor structure as claimed in claim 6 , wherein the bottom surface of the contact is lower than a bottom surface of a bottommost one of the nanostructures.
9. The semiconductor structure as claimed in claim 6 , further comprising:
a metal silicide layer formed in the source/drain structure, wherein a bottom portion of the metal silicide layer is lower than a bottom surface of a bottommost one of the nanostructures.
10. The semiconductor structure as claimed in claim 9 , wherein a top surface of the metal silicide layer is no higher than the top surface of the source/drain structure.
11. The semiconductor structure as claimed in claim 6 , wherein the source/drain structure comprises wider portions laterally extending between the inner spacers and thinner portions laterally covering sidewalls of the nanostructures.
12. A semiconductor structure, comprising:
a substrate;
nanostructures vertically stacked over one another over the substrate;
a gate structure wrapping around the nanostructures and extending in a first direction;
a source/drain structure attached to the nanostructures in a second direction different from the first direction;
inner spacers sandwiched between the nanostructures in a third direction; and
a contact overlapping the source/drain structure in the third direction, wherein a portion of the source/drain structure is sandwiched between a bottom portion of the contact and the inner spacers in the second direction.
13. The semiconductor structure as claimed in claim 12 , further comprising:
a gate spacer formed on a sidewall of the gate structure over the inner spacers, wherein the gate spacer is in direct contact with a top surface of a top most one of the inner spacers.
14. The semiconductor structure as claimed in claim 13 , wherein a dimension of the gate spacer is greater than a dimension of the inner spacer in the second direction.
15. The semiconductor structure as claimed in claim 13 , wherein an extending portion of the gate structure overlaps the gate spacer in the third direction.
16. The semiconductor structure as claimed in claim 15 , wherein the extending portion of the gate structure is in contact with a bottom surface of the gate spacer, a top surface of a topmost one of the nanostructures, and a sidewall of a topmost one of the inner spacers.
17. The semiconductor structure as claimed in claim 13 , wherein a dimension of an upper portion of the gate structure in contact with the gate spacer is smaller than a dimension of a lower portion of the gate structure in contact with the inner spacers in the second direction.
18. The semiconductor structure as claimed in claim 12 , wherein the bottom portion of the contact is lower than a bottom surface of a bottommost one of the nanostructures and is higher than a bottom surface of a bottommost one of the inner spacers.
19. The semiconductor structure as claimed in claim 12 , wherein the inner spacers have concave sidewalls in contact with the source/drain structure.
20. The semiconductor structure as claimed in claim 12 , wherein the nanostructures comprises:
a first nanostructure; and
a second nanostructure separated from the first nanostructure by the gate structure,
wherein the first nanostructure overlaps the second nanostructure in the third direction.