IP Library Granted Patent US 11,923,973
Granted Patent B2
US 11,923,973 · App. 17/962,023 · Granted Mar 5, 2024

Method and apparatus for encoding data using a polar code

Inventors: Huazi Zhang (Hangzhou, CN); Jiajie Tong (Hangzhou, CN); Rong Li (Hangzhou, CN); Jun Wang (Hangzhou, CN); Wen Tong (Ottawa, CA); Yiqun Ge (Ottawa, CA); Xiaocheng Liu (Hangzhou, CN)
Assignee: Huawei Technologies Co., Ltd.
H04L1/0009H03M13/11H03M13/13H03M13/611H03M13/616H03M13/6362H04L1/0041H04L1/0043H04L1/0061H04L1/0063H04L1/0065
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Quick Facts
Patent No.
US 11,923,973
App. No.
17/962,023
Granted
Mar 5, 2024
Kind
B2
Abstract

Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.

Claims (45)

1. A method comprising:

encoding, by an apparatus, information bits and three parity check bits generated based on a subset of the information bits, using a polar code to obtain encoded bits, the three parity check bits generated based on a length- 5 cyclic shift register, wherein the polar code is associated with a plurality of sub-channels, and the encoding comprises:

placing each of the information bits and the three parity check bits in a respective sub-channel of the plurality of sub-channels. wherein the placing comprises:

shifting the length- 5 cyclic shift register for each sub-channel of the plurality of sub-channels, and:

for placing each of the information bits, performing an XOR operatio n with a respective information bit value of the information bits and a bit value of the length-5 cyclic shift register, or

for placing each of the three parity check bits, retrieving a respective parity checkbit value of the three parity check bits from the length-5 cyclic shift register; and

outputting, by the apparatus, the encoded bits.

2. The method of claim 1 , wherein the plurality of sub-channels are ordered based on a reliability metric, and the placing comprises:

placing the three parity check bits in respective sub-channels of the plurality of sub-channels based on the reliability metric such that the respective sub-channels for the three parity check bits have lower reliabilities than sub-channels for the information bits.

3. The method of claim 1 , wherein the placing comprises:

placing at least one of the three parity check bits in a respective at least one sub-channel of the plurality of sub-channels, the respective at least one sub-channel being obtained from a subset of the plurality of sub-channels based on a minimum rowweight of the subset of the plurality of sub-channels.

4. A method, comprising:

receiving, by an apparatus from a second apparatus, a signal based on encodedbits, the encoded bits pro duced by encoding using a polar code, information bits and three parity check bits generated based on a subset of the information bits, and the three parity check bits generated based on a length- 5 cyclic shift register, wherein the polar code is asso ciated with a Plurality of sub-channels, wherein the encodedbits are further produced by placing each of the information bits and the three parity check bits in a respective sub-channel of the plurality of sub-channels, and whereinthe placing comprises:

shifting the length- 5 cyclic shift register for each sub-channel of the plurality of sub-channels, and:

for placing each of the information bits. performing an XOR operatio n with a respective information bit value of the information bits and a bit value of the length- 5 cyclic shift register, or

for placing each of the three parity check bits, retrieving a respective parity checkbit value of the three parity check bits from the length- 5 cyclic shift register; and

decoding, by the apparatus, the encoded bits.

5. The method of claim 4 , wherein the plurality of sub-channels are ordered based on a reliability metric, and the placing comprises:

placing the three parity check bits in respective sub-channels of the plurality of sub-channels based on the reliability metric such that the respective sub-channels for the three parity check bits have lower reliabilities than sub-channels for the information bits.

6. The method of claim 4 , wherein the placing comprises:

placing at least one of the three parity check bits in a respective at least one sub-channel of the plurality of sub-channels, the respective at least one sub-channel being obtained from a subset of the plurality of sub-channels based on a minimum rowweight of the subset of the plurality of sub-channels.

7. An apparatus comprising:

a processor;

a non-transitory computer readable storage medium storing instructions that, when executed by the processor, cause the apparatus to performing operations including:

encoding information bits and three parity check bits generated based on a subset of the information bits, using a polar code to obtain encoded bits, and the three parity check bits generated based on a length- 5 cyclic shift register, wherein the polar code is asso ciated with a plurality of sub-channels, and the encoding comprises:

placing each of the information bits and the three parity check bits in a respective sub-channel of the plurality of sub-channels, wherein the placing comprises:

shifting the length- 5 cyclic shift register for each sub-channel of the plurality of sub-channels, and:

for placing each of the information bits. performing an XOR op eration with a respective information bit value of the information bits and a bit value of the length- 5 cyclic shift register, or

for placing each of the three parity check bits, retrieving a respective parity checkbit value of the three parity check bits from the length- 5 cyclic shift register; and

output the encoded bits.

8. The apparatus of claim 7 , wherein the plurality of sub- channels are ordered based on a reliability metric, and the placing comprises:

placing the three parity check bits in respective sub-channels of the plurality of sub-channels based on the reliability metric such that the respective sub-channels for the three parity check bits have lower reliabilities than sub-channels for the information bits.

9. The apparatus of claim 7 , wherein the placing comprises:

placing at least one of the three parity check bits in a respective at least one sub-channel of the plurality of sub-channels, the respective at least one sub-channel being obtained from a subset of the plurality of sub-channels based on a minimum rowweight of the subset of the plurality of sub-channels.

10. An apparatus comprising:

a processor;

a non-transitory computer readable storage medium storing instructions that, when executed by the processor, cause the apparatus to performing operations including:

receiving, from another apparatus, a signal based on encodedbits, the encodedbits pro duced by encoding using a polar code, information bits and three parity check bits generated based on a subset of the information bits, and the three parity check bits generated based on a length- 5 cyclic shift register, wherein the polar code is associated with a plurality of sub-channels, wherein the encodedbits are further produced by placing each of the information bits and the three parity check bits in a respective sub-channel of the plurality of sub-channels, and wherein the placing comprises:

shifting the length-s cyclic shift register for each sub-channel of the plurality of sub-channels, and:

for placing each of the information bits, performing an XOR operatio n with a respective information bit value of the information bits and a bit value of the length- 5 cyclic shift register, or

for placing each of the three parity check bits, retrieving a respective parity checkbit value of the three parity check bits from the length- 5 cyclic shift register; and

decoding the encoded bits.

11. The apparatus of claim 10 , wherein the plurality of sub- channels are ordered based on a reliability metric, and the placing comprises:

placing the three parity check bits in respective sub-channels of the plurality of sub-channels based on the reliability metric such that the respective sub -channels for the three parity check bits have lower reliabilities than sub-channels for the information bits.

12. The apparatus of claim 10 , wherein the placing comprises placing at least one of the three parity check bits in a respective at least one sub-channel of the plurality of sub-channels, the respective at least one sub-channel being obtained from a subset of the plurality of sub-channels based on a minimum row weight of the subset of the plurality of sub-channels.

Continuity (10)
Continuation 16892731 · Jun 4, 2020
Continuation 16163169 · Oct 17, 2018
Continuation 15699976 · Sep 8, 2017
Provisional Application 62433127 · Dec 12, 2016
Provisional Application 62432416 · Dec 9, 2016
Provisional Application 62432448 · Dec 9, 2016
Provisional Application 62402862 · Sep 30, 2016
Provisional Application 62396618 · Sep 19, 2016
Provisional Application 62395312 · Sep 15, 2016
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