IP Library › Granted Patent US 11,929,340
Granted Patent B2
US 11,929,340 · App. 17/394,213 · Granted Mar 12, 2024

Arrangement of power-grounds in package structures

Inventors: Ting-Yu Yeh (Hsinchu, TW); Chun-Hua Chang (Zhubei, TW); Fong-Yuan Chang (Hsinchu, TW); Jyh Chwen Frank Lee (Palo Alto, CA)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L24/20H01L24/19H01L21/568H01L24/13H01L2224/13024H01L2224/19H01L2224/221
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Quick Facts
Patent No.
US 11,929,340
App. No.
17/394,213
Granted
Mar 12, 2024
Kind
B2
Abstract

A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

Claims (39)

1. A structure comprising:

a device die;

an encapsulant encapsulating the device die therein;

a redistribution structure over and electrically connected to the device die, wherein the redistribution structure comprises a bottom layer and a plurality of upper layers over the bottom layer, and wherein the redistribution structure comprises:

a first power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers;

a second power-ground macro extending from the topmost layer in the plurality of upper layers to the bottommost layer in the plurality of upper layers;

at least one first conductive feature in the bottom layer and overlapped by the first power-ground macro; and

at least one second conductive feature in the bottom layer and overlapped by the second power-ground macro, wherein patterns of the at least one first conductive feature are different from the at least one second conductive feature.

2. The structure of claim 1 , wherein the at least one first conductive feature comprises a first plurality of conductive features, the at least one second conductive feature comprises a second plurality of conductive features, and a first total count of the first plurality of conductive features is different from a second total count of the second plurality of conductive features.

3. The structure of claim 1 , wherein the at least one first conductive feature comprises a first metal pad electrically disconnected from the first power-ground macro.

4. The structure of claim 1 , wherein the topmost layer comprises a solder region.

5. The structure of claim 1 , wherein the bottom layer is in contact with a metal pad in the device die.

6. The structure of claim 1 , wherein both of the first power-ground macro and the second power-ground macro are VDD macros.

7. The structure of claim 1 , wherein both of the first power-ground macro and the second power-ground macro are VSS macros.

8. The structure of claim 1 , wherein the first power-ground macro comprises a plurality of metal plates, each in one of the plurality of upper layers, and a plurality of vias in each of the plurality of upper layers, and wherein the plurality of metal plates in the first power-ground macro have identical patterns, locations, and sizes as corresponding ones of the plurality of metal plates in the second power-ground macro.

9. The structure of claim 1 , wherein the first power-ground macro comprises a plurality of metal plates, and edges of the plurality of metal plates are vertically aligned.

10. The structure of claim 1 , wherein the redistribution structure further comprises an additional layer over the bottom layer and under the plurality of upper layers, and wherein the redistribution structure further comprises a metal pad in the additional layer, and the metal pad is overlapped by, and is electrically disconnected from, the first power-ground macro.

11. A structure comprising:

a redistribution structure comprising a bottom layer and a plurality of upper layers over the bottom layer, wherein the redistribution structure comprises:

a first power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers; and

a first metal pad in the bottom layer and overlapped by the first power-ground macro, wherein the first metal pad is electrically disconnected from the first power-ground macro.

12. The structure of claim 11 further comprising a second metal pad in the bottom layer and overlapped by the first power-ground macro, wherein the second metal pad is electrically connected to the first power-ground macro.

13. The structure of claim 11 further comprising a device die overlapped by the first power-ground macro, wherein the device die further comprises a second metal pad physically bonding to the first metal pad.

14. The structure of claim 11 further comprising:

a second power-ground macro extending from the topmost layer in the plurality of upper layers to the bottommost layer in the plurality of upper layers, wherein the second power-ground macro is identical to the first power-ground macro; and

a second metal pad in the bottom layer and overlapped by the second power-ground macro, wherein the second metal pad is electrically connected to the second power-ground macro.

15. The structure of claim 14 , wherein a first total number of metal pads in the bottom layer and overlapped by the first power-ground macro is different from a second total number of metal pads in the bottom layer and overlapped by the second power-ground macro.

16. A structure comprising:

a device die comprising metal pads therein;

an encapsulant encapsulating the device die therein, wherein top surfaces of the encapsulant and the metal pads are coplanar; and

a redistribution structure over the device die and the encapsulant, wherein the redistribution structure comprises a bottom layer in contact with the metal pads, and a plurality of upper layers over the bottom layer, and wherein the redistribution structure comprises:

a first power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers; and

a first metal pad in the bottom layer and overlapped by the first power-ground macro, wherein the first metal pad is electrically disconnected from the first power-ground macro.

17. The structure of claim 16 , wherein the redistribution structure further comprises:

a second power-ground macro extending from the topmost layer in the plurality of upper layers to the bottommost layer in the plurality of upper layers; and

a second metal pad in the bottom layer and overlapped by the second power-ground macro, wherein the second metal pad is electrically connected to the second power-ground macro.

18. The structure of claim 16 , wherein the first power-ground macro comprises a solder region in the topmost layer in the plurality of upper layers.

19. The structure of claim 16 , wherein the plurality of upper layers comprise four layers.

20. The structure of claim 16 , wherein the first power-ground macro comprises a VDD macro.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2021
From: YEH, TING-YU; CHANG, CHUN-HUA; CHANG, FONG-YUAN; LEE, JYH CHWEN FRANK
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 057083/0779 →
Continuity (2)
Provisional Application 63139940 · Jan 21, 2021
Related Publication 20220230981A1 · Jul 21, 2022