Transistor gate structure and method of forming
View Patent ↗A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nano structure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.
1. A device comprising:
a first nanostructure;
a second nanostructure over the first nanostructure;
a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and
a gate electrode over the high-k gate dielectric, wherein the gate electrode comprises:
a first work function metal around the first nanostructure and the second nanostructure, the first work function metal comprising a seam between a first portion of the first work function metal and a second portion of the first work function metal, wherein the seam is disposed between the first nanostructure and the second nanostructure; and
a tungsten layer over the first work function metal.
2. The device of claim 1 , wherein the gate electrode further comprises a fill material over the tungsten layer, the fill material having a higher concentration of fluorine than the tungsten layer.
3. The device of claim 2 , wherein the fill material comprises tungsten.
4. The device of claim 1 , wherein the first work function metal is a p-type work function metal.
5. The device of claim 1 , wherein the first work function metal is free of fluorine.
6. The device of claim 1 , wherein the gate electrode further comprises an adhesion layer between the tungsten layer and the first work function metal.
7. A transistor comprising:
a first nanostructure over a semiconductor substrate;
a second nanostructure over the first nanostructure;
a gate dielectric surrounding the first nanostructure and the second nanostructure;
a gate electrode over the gate dielectric, wherein the gate electrode comprises:
a work function metal around the first nanostructure and the second nanostructure;
a barrier layer over the work function metal, the barrier layer comprising tungsten; and
a fill metal over the barrier layer, the fill metal comprising tungsten, wherein the fill metal has a higher concentration of fluorine than the barrier layer; and
a gate spacer on a sidewall of the gate electrode, wherein a bottom surface of the gate spacer contacts a top surface of the second nanostructure.
8. The transistor of claim 7 further comprising an adhesion layer between the barrier layer and the fill metal.
9. The transistor of claim 7 , wherein a thickness of the barrier layer is in a range of 15 Å to 90 Å.
10. The transistor of claim 7 , wherein the barrier layer is free of fluorine, and wherein the work function metal is free of fluorine.
11. The transistor of claim 7 , wherein the work function metal is a p-type work function metal, and wherein a first portion of the work function metal meets a second portion of the work function metal at a seam between the first nanostructure and the second nanostructure.
12. The transistor of claim 7 , wherein the barrier layer and the fill metal each comprise tungsten.
13. The transistor of claim 7 further comprising an interfacial layer under the gate dielectric, the interface layer surrounding the first nanostructure and the second nanostructure, and the gate dielectric comprises a high-k material.
14. A method comprising:
depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure is disposed over the second nanostructure;
depositing a work function metal over the gate dielectric, wherein the work function metal completely fills a region extending from a first portion of the gate dielectric surrounding the first nanostructure to a second portion of the gate dielectric surrounding the second nanostructure;
depositing a barrier layer over the work function metal, wherein depositing the barrier layer comprises a first atomic layer deposition (ALD) process; and
depositing a fill metal over the barrier layer, wherein depositing the fill metal comprises using a fluorine-comprising precursor.
15. The method of claim 14 , wherein the first ALD process does not use any fluorine-comprising precursors.
16. The method of claim 15 , wherein the first ALD process comprises using a combination of W x Cl y and H 2 as precursors.
17. The method of claim 14 , wherein depositing the fill metal comprises a chemical vapor deposition (CVD) process, and wherein the fluorine-comprising precursor is WF 6 .
18. The method of claim 17 , wherein depositing the fill metal further comprises a second ALD process performed before the CVD process, and wherein the second ALD process comprises using WF 6 as a precursor.
19. The method of claim 14 further comprising depositing an adhesion layer between the work function metal and the barrier layer.
20. The method of claim 14 , wherein the barrier layer and the fill metal each comprise tungsten.