Semiconductor structure and method for manufacturing thereof
View Patent ↗A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.
1. A semiconductor structure, comprising:
a substrate having a first surface;
a conductive region in the substrate;
a first insulation layer over the first surface;
a second insulation layer over the first insulation layer;
a gate structure over the first surface of the substrate and surrounded by the first insulation layer;
a low-k spacer between a sidewall of the gate structure and an etch stop layer, the etch stop layer between the low-k spacer and the first insulation layer, wherein the low-k spacer has a first dielectric constant, the etch stop layer has a second dielectric constant, and the first insulation layer has a third dielectric constant, wherein the first dielectric constant is smaller than the second dielectric constant and the third dielectric constant, wherein the low-k spacer comprises SiOCN and has a concentration of silicon (Si) in the SiOCN is between about 25% and 35%, wherein a concentration of oxygen (O) in the SiOCN is between about 4% and 6%, wherein a concentration of carbon (C) in the SiOCN is between about 35% and 45%, and wherein a concentration of nitrogen (N) is in the range from about 15% to about 25%;
a gate contact landed on a top surface of the gate structure; and
a conductive region contact over the conductive region and surrounded by the first insulation layer and the second insulation layer, a top surface of the conductive region contact being leveled with a top surface of the second insulation layer;
wherein a proximity distance between a sidewall of the gate contact and the conductive region contact along the top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm.
2. The semiconductor structure of claim 1 , wherein the gate contact is landed on the gate structure and the low-k spacer.
3. The semiconductor structure of claim 2 , wherein the gate contact shifted from a center of the gate structure by a shift distance smaller than the proximity distance.
4. The semiconductor structure of claim 1 , wherein the substrate further has an isolation region at the first surface extending under the conductive region and the gate structure, and the gate structure is in contact with the isolation region.
5. The semiconductor structure of claim 1 , wherein a top surface of the etch stop layer, a top surface of the low-k spacer, and the top surface of the gate structure are coplanar.
6. The semiconductor structure of claim 5 , wherein a bottom surface of the gate contact is in contact with the top surface of the low-k spacer.
7. The semiconductor structure of claim 6 , wherein the bottom surface of the gate contact is further in contact with the top surface of the etch stop layer.
8. A semiconductor structure, comprising:
a substrate having a first surface;
a conductive region in the substrate;
a first insulation layer over the first surface;
a second insulation layer over the first insulation layer;
a gate structure over the first surface of the substrate and surrounded by the first insulation layer;
a low-k spacer between a sidewall of the gate structure and the first insulation layer, wherein a dielectric constant of the low-k spacer is between about 2 and about 3;
a gate contact extending through the second insulation layer and landing on a top surface of the gate structure and a top surface of the low-k spacer, wherein the gate contact includes a sidewall extending from a first end region to a second end region and a recap layer disposed on a middle region of the sidewall between the first end region and the second end region wherein the first and second end regions are free of the recap layer; and
a conductive region contact over the conductive region and surrounded by the first insulation layer and the second insulation layer.
9. The semiconductor structure of claim 8 , wherein the low-k spacer comprises SiOCN.
10. The semiconductor structure of claim 8 , wherein a distance between a sidewall of the gate contact and a top surface of the conductive region contact is smaller than about 7 nm.
11. The semiconductor structure of claim 8 , wherein a bottom dimension of the gate contact is in a range of from about 14 nm to about 18 nm.
12. The semiconductor structure of claim 8 , wherein a top surface of the first insulation layer is coplanar with the top surface of the gate structure.
13. The semiconductor structure of claim 8 , wherein a top surface of the second insulation layer is coplanar with a top surface of the conductive region contact.
14. The semiconductor structure of claim 13 , wherein a smallest distance between the gate contact and the conductive region contact is aligned to the top surface of the second insulation layer.
15. The semiconductor structure of claim 8 , wherein a center of the gate contact is shifting away from a center of the gate structure in a shift distance less than about 4 nm.
16. A semiconductor structure, comprising:
an epitaxial region over a substrate;
a first insulation layer over the epitaxial region and the substrate;
a gate structure over the substrate, wherein the gate structure includes a centerline defined in a first cross-sectional view;
a spacer element disposed on sidewalls of the gate structure, wherein the spacer element is SiOCN;
a first contact extending through the first insulation layer to interface a top surface of the gate structure and a top surface of the spacer element, wherein the first contact has a centerline defined in the first cross-sectional view that is displaced a first shift distance from the centerline of the gate structure, and wherein the first contact includes a sidewall extending from a first terminal end to a second terminal end and a recap layer disposed on a middle region of the sidewall, wherein a first end region adjacent the first terminal end and a second end region adjacent the second terminal end are free of the recap layer; and
a second contact over and extending towards the epitaxial region.
17. The semiconductor structure of claim 16 , wherein the centerline is substantially perpendicular to a top surface of the substrate.
18. The semiconductor structure of claim 16 , wherein a concentration of silicon (Si) in the SiOCN is between about 25% and 35%, wherein a concentration of oxygen (O) in the SiOCN is between about 4% and 6%, wherein a concentration of carbon (C) in the SiOCN is between about 35% and 45%, and wherein a concentration of nitrogen (N) is in the range from about 15% to about 25%.
19. The semiconductor structure of claim 16 , wherein the recap layer includes SiN.