IP Library › Granted Patent US 11,939,678
Granted Patent B2
US 11,939,678 · App. 17/533,579 · Granted Mar 26, 2024

Method of making a semiconductor manufacturing apparatus member

Inventors: Yasutaka Nitta (Kitakyushu, JP); Takuma Wada (Kitakyushu, JP)
Assignee: TOTO LTD.
C23C24/04H01J37/321H01J37/32477H01J37/32715C23C16/4404H01J2237/2007H01J2237/3341H01L21/68757
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Quick Facts
Patent No.
US 11,939,678
App. No.
17/533,579
Granted
Mar 26, 2024
Kind
B2
Abstract

A method of making a semiconductor manufacturing apparatus member includes a step of preparing an aluminum base having an alumite layer having a porous columnar structure at an upper surface thereof. The alumite layer is an anodic oxidation film, and a Young's modulus of the alumite layer is between 90 GPa and 120 GPa. The method also includes a step of forming a particle-resistant layer on the alumite layer by aerosol deposition, in which an aerosol containing fine particles of a brittle material dispersed in a gas is ejected from a nozzle to impact against a surface of the alumite layer, wherein the particle-resistant layer includes a polycrystalline ceramic; and wherein, when the resulting semiconductor manufacturing apparatus member is exposed to a plasma in a reference plasma resistance test, the particle-resistant layer has an arithmetic average height Sa of 0.060 or less after the reference plasma test is completed.

Claims (8)

1. A method of making a semiconductor manufacturing apparatus member having particle resistance, comprising steps of:

a) preparing a base comprising aluminum and having an alumite layer which is an anodic oxidation film at an upper surface of the base, wherein the alumite layer has a porous columnar structure, wherein a Young's modulus of the alumite layer is greater than 90 GPa and is less than or equal to 120 GPa; and

b) forming a particle-resistant layer of Y 2 O 3 on the alumite layer by aerosol deposition, in which an aerosol containing fine particles of a brittle material dispersed in a gas is ejected from a nozzle to impact against a surface of the alumite layer, wherein the particle-resistant layer includes a polycrystalline ceramic;

wherein the particle-resistant layer has an arithmetic average height Sa of 0.060 μm or less after a reference plasma test is completed in which the semiconductor manufacturing apparatus member is exposed to a plasma.

2. The method of claim 1 , wherein an average crystallite size of the polycrystalline ceramic is in a range of 3 nm to 50 nm.

3. The method of claim 2 , wherein the average crystallite size is in a range of 3 nm to 30 nm.

4. The method of claim 1 , further comprising a step of smoothing the alumite layer prior to applying the particle-resistant layer thereto, so that the front surface of the alumite layer has an arithmetic average roughness Ra of 0.2 μm or less.

5. The method of claim 4 , wherein the front surface of the alumite layer has an arithmetic average roughness Ra of 0.1 μm or less after smoothing.

Priority Claims (2)
JP 2019-033545 · Feb 27, 2019 · national
JP 2019-222020 · Dec 9, 2019 · national
Continuity (2)
Division 16802059 · Feb 26, 2020
Related Publication 20220139676A1 · May 5, 2022
Cited By (2)
US 12,709,807 US 12,738,460