Package and manufacturing method thereof

1. A package, comprising:

a first die having a first interconnection structure, wherein the first interconnection structure comprises a first capacitor embedded therein;

a second die having a second interconnection structure, wherein the second interconnection structure comprises a second capacitor embedded therein, the first interconnection structure faces the second interconnection structure, the second die is stacked on the first die, and the first capacitor is electrically connected to the second capacitor; and

an encapsulant laterally encapsulating the second die.

2. The package of claim 1 , wherein the first die further comprises:

a first bonding layer disposed over the first interconnection structure;

a passivation layer sandwiched between the first interconnection structure and the first bonding layer;

conductive pads embedded in the passivation layer; and

bonding vias penetrating through the passivation layer to connect the first bonding layer and the first capacitor.

3. The package of claim 2 , wherein the first capacitor comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, one of the bonding vias is directly in contact with the top metal layer, and another one of the bonding vias is directly in contact with the bottom metal layer.

4. The package of claim 3 , wherein the first interconnection structure comprises dielectric layers and conductive patterns embedded in the dielectric layers, and a material of the dielectric layers of the first interconnection structure is different from a material of the insulating layer of the first capacitor.

5. The package of claim 2 , wherein the first capacitor comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, the insulating layer and the top metal layer comprise an opening exposing the bottom metal layer, and at least one of the bonding vias extends into the opening to contact the bottom metal layer.

6. The package of claim 2 , wherein the first die further comprises a third capacitor embedded in the passivation layer, and the third capacitor is electrically connected to the first capacitor and the second capacitor.

7. The package of claim 1 , further comprising:

a redistribution structure disposed on the second die and the encapsulant; and

through insulating vias (TIV) electrically connecting the first die and the redistribution structure.

8. The package of claim 7 , wherein the second die further comprises a semiconductor substrate and through semiconductor vias (TSV) penetrating through the semiconductor substrate, and the TSVs electrically connect the second interconnection structure and the redistribution structure.

9. A package, comprising:

a first die, comprising:

a first interconnection structure; and

first bonding vias at least partially embedded in the first interconnection structure;

a second die stacked on the first die, comprising:

a second interconnection structure; and

second bonding vias at least partially embedded in the second interconnection structure;

a passive device, comprising a first portion and a second portion electrically connected to the first portion, wherein the first portion is embedded in the first interconnection structure, the second portion is embedded in the second interconnection structure, the first portion comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, one of the first bonding vias is directly in contact with the top metal layer, and another one of the first bonding vias is directly in contact with the bottom metal layer; and

an encapsulant laterally encapsulating the second die.

10. The package of claim 9 , wherein the first interconnection structure comprises dielectric layers and conductive patterns embedded in the dielectric layers, and a material of the dielectric layers of the first interconnection structure is different from a material of the insulating layer.

11. The package of claim 9 , wherein the insulating layer and the top metal layer comprise an opening exposing the bottom metal layer, and the another one of the first bonding vias extends into the opening to contact the bottom metal layer.

12. The package of claim 9 , further comprising:

a redistribution structure disposed on the second die and the encapsulant;

through insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs electrically connect the first die and the redistribution structure.

13. The package of claim 12 , wherein the first die further comprises first bonding pads over the first interconnection structure, the second die further comprises second bonding pads over the second interconnection structure, the first bonding vias are connected to the first bonding pads, the second bonding vias are connected to the second bonding pads, sidewalls of each first bonding pad are aligned with sidewalls of the corresponding second bonding pad.

14. The package of claim 13 , wherein the first die further comprises third bonding pads levelled with the first bonding pads, and the TIVs are in direct contact with the third bonding pads.

15. A manufacturing method of a package, comprising:

providing a wafer substrate having a first interconnection structure, first bonding vias, and a first bonding layer disposed over the first interconnection structure, wherein a first capacitor is formed in the first interconnection structure, and the first bonding vias electrically connect the first bonding layer and the first capacitor;

providing a die having a second interconnection structure, second bonding vias, and a second bonding layer disposed over the second interconnection structure, wherein a second capacitor is formed in the second interconnection structure, and the second bonding vias electrically connect the second bonding layer and the second capacitor;

bonding the first bonding layer of the wafer substrate to the second bonding layer of the die such that the first capacitor is electrically connected to the second capacitor; and

laterally encapsulating the die by an encapsulant.

16. The method of claim 15 , wherein the first capacitor comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, the first interconnection structure comprises dielectric layers and conductive patterns embedded in the dielectric layers, and the bottom metal layer of the first capacitor and one of the conductive patterns are simultaneously formed.

17. The method of claim 16 , wherein providing the wafer substrate further comprises:

forming an opening in the top metal layer and the insulating layer to expose the bottom metal layer, wherein at least one of the first bonding vias extends into the opening to contact the bottom metal layer.

18. The method of claim 15 , wherein providing the wafer substrate further comprises:

forming a third capacitor over the first interconnection structure; and

forming a first passivation layer on the first interconnection structure to cover the third capacitor, and at least one of the first bonding vias connects the first bonding layer and the third capacitor.

19. The method of claim 18 , wherein providing the dies further comprises:

forming a fourth capacitor over the second interconnection structure; and

forming a second passivation layer on the second interconnection structure to cover the fourth capacitor, and at least one of the second bonding vias connects the second bonding layer and the fourth capacitor.

20. The method of claim 15 , further comprising:

forming a redistribution structure over the die and the encapsulant;

forming through insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs electrically connect the wafer substrate and the redistribution structure.