Source/drain epitaxial layer profile
View Patent ↗The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
1. A semiconductor structure, comprising:
a semiconductor layer on a substrate;
an isolation region surrounding the semiconductor layer;
an epitaxial stack partially disposed in the semiconductor layer; and
a germanium-doped (Ge-doped) structure on the semiconductor layer and between the isolation region and the epitaxial stack, wherein a depth of the epitaxial stack is equal to or greater than a depth of the Ge-doped structure.
2. The semiconductor structure of claim 1 , further comprising:
a gate structure over the semiconductor layer and adjacent to the epitaxial stack, wherein a distance between the gate structure and the Ge-doped structure is about 40 nm or greater.
3. The semiconductor structure of claim 1 , wherein the Ge-doped structure has a lattice constant greater than that of silicon.
4. The semiconductor structure of claim 1 , wherein the Ge-doped structure is in contact with a top surface of the semiconductor layer.
5. The semiconductor structure of claim 1 , wherein the Ge-doped structure extends about 5 nm to about 25 nm into the isolation region.
6. The semiconductor structure of claim 1 , wherein the epitaxial stack has a substantially horizontal top surface.
7. The semiconductor structure of claim 1 , wherein the epitaxial stack has a substantial uniform thickness.
8. The semiconductor structure of claim 1 , wherein the epitaxial stack comprises one or more silicon germanium layers.
9. A semiconductor structure, comprising:
a semiconductor layer over a substrate, wherein the semiconductor layer comprises a germanium-doped (Ge-doped) region;
an epitaxial stack partially disposed in the semiconductor layer and surrounded by the Ge-doped region; and
an isolation region surrounding the semiconductor layer, wherein the isolation region is in contact with the semiconductor layer and the Ge-doped region.
10. The semiconductor structure of claim 9 , wherein the Ge-doped region separates the epitaxial stack and the isolation region.
11. The semiconductor structure of claim 9 , wherein a height of the epitaxial stack from a top surface of the semiconductor layer to a bottom surface of the epitaxial stack is equal to or greater than a height of the Ge-doped region.
12. The semiconductor structure of claim 9 , wherein the Ge-doped region has a width between about 5 nm and about 25 nm.
13. The semiconductor structure of claim 9 , wherein the epitaxial stack has a substantially horizontal top surface.
14. The semiconductor structure of claim 9 , further comprising:
a gate structure disposed over the semiconductor layer and the isolation region; and
a spacer on sidewalls of the gate structure, wherein the spacer is interposed between the gate structure and the epitaxial stack.
15. The semiconductor structure of claim 14 , wherein a distance between the gate structure and the Ge-doped region is equal to or greater than a thickness of the spacer on the sidewalls of the gate structure.
16. A semiconductor structure, comprising:
a substrate with a semiconductor layer thereon, wherein the semiconductor layer comprises a germanium-doped (Ge-doped) region;
a first gate structure with a first sidewall spacer disposed on the semiconductor layer;
a second gate structure with a second sidewall spacer disposed on the semiconductor layer, wherein the first and second gate structures are parallel to each other; and
an epitaxial layer disposed on the semiconductor layer and between the first and second gate structures, wherein the epitaxial layer is surrounded by the Ge-doped region and the first and second sidewall spacers.
17. The semiconductor structure of claim 16 , wherein a thickness the Ge-doped region is between about 5 nm and about 25 nm.
18. The semiconductor structure of claim 16 , further comprising an isolation region surrounding the semiconductor layer, wherein the Ge-doped region separates the isolation region and the epitaxial layer.
19. The semiconductor structure of claim 16 , wherein a distance between the Ge-doped region and the first gate structure is equal to or greater than a thickness of the first sidewall spacer.
20. The semiconductor structure of claim 16 , wherein a depth of the epitaxial layer extending into the semiconductor layer is equal to or greater than a depth of the Ge-doped region.