Source/drain epitaxial layer profile
View Patent ↗The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
1 . A method, comprising:
forming an isolation region adjacent to a semiconductor layer;
doping, with germanium (Ge), a portion of the semiconductor layer and a portion of the isolation region to form a Ge-doped region that extends from the semiconductor layer to the isolation region;
etching the Ge-doped region in the semiconductor layer to form openings, wherein the openings comprise at least one common sidewall with the Ge-doped region in the isolation region; and
forming a silicon germanium (SiGe) epitaxial stack in the openings.
2 . The method of claim 1 , further comprising, prior to etching the Ge-doped region in the semiconductor layer, performing an anneal process to convert the Ge-doped region in the isolation region to a SiGe structure.
3 . The method of claim 2 , wherein forming the SiGe epitaxial stack comprises growing the SiGe epitaxial stack on a sidewall of the SiGe structure in the isolation region.
4 . The method of claim 1 , wherein doping with the Ge comprises implanting a Ge dopant dose between about 1×10 16 ions/cm 2 and about 1×10 18 ions/cm 2 .
5 . The method of claim 1 , wherein etching the Ge-doped region in the semiconductor layer to form the openings comprises forming the openings with a bottom surface lower than a bottom surface of the Ge-doped region in the isolation region.
6 . The method of claim 1 , wherein forming the SiGe epitaxial stack comprises forming the SiGe epitaxial stack with a depth equal to or greater than a depth of the Ge-doped region in the isolation region.
7 . The method of claim 1 , further comprising, prior to etching the Ge-doped region in the semiconductor layer, masking an entire top surface of the isolation region.
8 . The method of claim 1 , wherein etching the Ge-doped region in the semiconductor layer comprises removing the Ge-doped region from the semiconductor layer.
9 . A method, comprising:
forming an isolation region on side surfaces of a fin structure;
forming a gate structure on a first portion of the fin structure;
forming a first masking structure to cover the gate structure and a second portion of the fin structure, wherein the second portion is wider than the first portion;
forming a germanium-doped (Ge-doped) region in a third portion of the fin structure, wherein the third portion of the fin structure extends between the first masking structure and the isolation region;
forming a second masking structure to cover the isolation region and an area of the Ge-doped region in the third portion of the fin structure adjacent to the isolation region;
removing the Ge-doped region in the third portion of the fin structure between the gate structure and the second masking structure to form an opening in the fin structure; and
growing an epitaxial stack in the opening, wherein the epitaxial stack is in contact with the area of the Ge-doped region in the third portion of the fin structure.
10 . The method of claim 9 , wherein removing the Ge-doped region to form the opening comprises forming the opening narrower than the third portion of the fin structure.
11 . The method of claim 9 , wherein growing the epitaxial stack comprises growing a silicon-germanium (SiGe) stack in contact with un-etched portions of the Ge-doped region in the third portion of the fin structure.
12 . The method of claim 9 , wherein forming the Ge-doped region in the third portion of the fin structure comprises forming the Ge-doped region abutting side surfaces of the isolation region.
13 . The method of claim 9 , further comprising, prior to forming the second masking structure:
removing the first masking structure; and
forming gate spacers on sidewall surfaces of the gate structure, wherein the gate spacers extend between the sidewall surfaces of the gate structure and the third portion of the fin structure.
14 . The method of claim 9 , wherein growing the epitaxial stack comprises forming the epitaxial stack in contact with a depth equal to or greater than a depth of the Ge-doped region in the third portion of the fin structure.
15 . The method of claim 9 , wherein removing the Ge-doped region in the third portion of the fin structure comprises leaving a portion of the Ge-doped region covered by the second masking structure un-etched.
16 . The method of claim 9 , wherein growing the epitaxial stack comprises interposing un-etched portions of the Ge-doped region in the third portion of the fin structure between the epitaxial stack and the isolation region.
17 . A method, comprising:
forming an isolation region adjacent to a semiconductor layer;
forming a gate structure on the semiconductor layer;
forming a germanium-doped (Ge-doped) region in the semiconductor layer between the gate structure and the isolation region;
etching a first portion of the Ge-doped region in the semiconductor layer to form an opening, wherein a second portion of the Ge-doped region remains between the opening and the isolation region; and
forming an epitaxial stack in the opening abutting the second portion of the Ge-doped region in the semiconductor layer.
18 . The method of claim 17 , wherein etching the first portion of the Ge-doped region in the semiconductor layer to form the opening comprises etching a portion of the semiconductor layer below the Ge-doped region.
19 . The method of claim 17 , wherein forming the Ge-doped region comprises forming the Ge-doped region spaced apart from the gate structure.
20 . The method of claim 17 , wherein forming the epitaxial stack comprises forming one or more silicon-germanium (Si-Ge) layers in contact with the second portion of the Ge-doped region in the semiconductor layer.