Semiconductor memory device and methods of manufacturing and operating the same
A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.
1. A method of operating a semiconductor memory device, the method comprising:
performing a program operation on a plurality of memory cells each including a channel layer, a tunnel insulating layer, an emission preventing layer, a charge storage layer, a blocking insulating layer, and a compensation charge storage layer in response to a program command;
suspending the program operation in response to a suspend command received from outside of the semiconductor memory device, and applying a positive voltage to bit lines or a source line, connected to the memory cells, during a suspend period; and
re-performing the suspended program operation in response to a resume command received from outside of the semiconductor memory device.
2. The method of claim 1 , wherein gates of the plurality of memory cells are controlled to have a ground level during the suspend period, and
wherein charges are trapped in the compensation charge storage layer of each of the plurality of memory cells.