Coordinating power transitions between a smart interconnect and heterogeneous components
Described is an apparatus comprising a semiconductor interconnect substrate and an interface. The semiconductor interconnect substrate may be electrically coupled to one or more components mounted thereon. The interface may be operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode.
1. A non-transitory machine-readable storage media having machine-readable instructions stored thereon, that when executed, cause one or more machines, to perform a method comprising:
placing a semiconductor interconnect substrate into a power-up mode, the semiconductor interconnect substrate being electrically coupled to one or more components mounted thereon; and
applying a configuration command set to the one or more components in a normal operation mode subsequent to the power-up mode, wherein applying the configuration command set comprises sequencing configuration of the one or more components based on configuration register values associated with a boot configuration, wherein the configuration command set encompasses a resistor disconnection command that establishes a strapping or logical value on an interface of a component, of the one or more components, with a plurality of strapping pins coupled to the component, and wherein the plurality of strapping pins are operable to configure a static behavior of an interconnect of the semiconductor interconnect substrate.
2. The non-transitory machine-readable storage media of claim 1 , having machine-readable instructions stored thereon, that when executed, cause the one or more machines, to perform a further method comprising:
sequencing power of a microcontroller unit in response to sequencing the configuration of the one or more components.
3. The non-transitory machine-readable storage media of claim 1 , having machine-readable instructions stored thereon, that when executed, cause the one or more machines, to perform a further method comprising:
establishing a plurality of interface states for the one or more components.
4. The non-transitory machine-readable storage media of claim 1 , wherein the configuration command set encompasses a triggering event to apply a plurality of interface states substantially simultaneously.
5. The non-transitory machine-readable storage media of claim 1 , wherein the configuration command set is a second configuration command set, and wherein the machine-readable storage media has machine-readable instructions stored thereon, that when executed, cause the one or more machines, to perform a further method comprising:
applying a first configuration command set to the one or more components in the power-up mode.
6. The non-transitory machine-readable storage media of claim 1 having machine-readable instructions stored thereon, that when executed, cause the one or more machines, to perform a further method comprising:
electrically disconnecting a mounted component from the semiconductor interconnect substrate.
7. The non-transitory machine-readable storage media of claim 1 , wherein the semiconductor interconnect substrate includes within it a logic to handle sequence and/or control of power functions for the one or more components, wherein the semiconductor interconnect substrate includes within it a microcontroller unit.
8. The non-transitory machine-readable storage media of claim 7 , wherein the logic, to handle sequence and/or control of power functions for the one or more components, comprises: a power management unit; a power kernel and controller coupled to the power management unit, and a memory coupled to the power kernel and controller.
9. The non-transitory machine-readable storage media of claim 7 having machine-readable instructions stored thereon, that when executed, cause the one or more machines, to perform a further method comprising:
sequencing one or more reset signals to reset the microcontroller unit.
10. The non-transitory machine-readable storage media of claim 7 , wherein the semiconductor interconnect substrate includes within it a microelectromechanical system-based temperature compensated crystal oscillator coupled to the microcontroller unit.