IP Library Granted Patent US 11,960,433
Granted Patent B2
US 11,960,433 · App. 17/483,560 · Granted Apr 16, 2024

Techniques to transfer data among hardware devices

Inventors: Kiran Kumar Modukuri (Santa Clara, CA); Christopher J. Newburn (South Beloit, IL); Saptarshi Sen (San Jose, CA); Akilesh Kailash (San Jose, CA); Sandeep Joshi (Campbell, CA)
Assignee: NVIDIA Technologies, Inc.
G06F13/4282G06F13/28G06F13/4022G06F15/173G06F15/17362G06F2213/0026
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Quick Facts
Patent No.
US 11,960,433
App. No.
17/483,560
Granted
Apr 16, 2024
Kind
B2
Abstract

Apparatuses, systems, and techniques to route data transfers between hardware devices. In at least one embodiment, a path over which to transfer data from a first hardware component of a computer system to a second hardware component of a computer system is determined based, at least in part, on one or more characteristics of different paths usable to transfer the data.

Claims (30)

1. A processor, comprising:

one or more circuits to perform an application programming interface (API) to select one or more interconnects to be used to transfer information among two or more computing resources based, at least in part, on one or more performance metrics corresponding to the one or more interconnects.

2. The processor of claim 1 , wherein the API is to generate a plurality of values corresponding to a plurality of dynamic component conditions, and select the one or more interconnects based, at least in part, on the plurality of values.

3. The processor of claim 1 , wherein the API is to cause the information to be transferred based, at least in part, on whether a bandwidth of a first communication path is higher than a bandwidth of a path that traverses an interconnect not included in the first communication path.

4. The processor of claim 1 , wherein the API is to cause the information to be transferred based, at least in part, on a predetermined cost function that is based, at least in part, on one or more of bandwidth and latency.

5. The processor of claim 1 , wherein one or more of the two or more computing resources is a graphics processing unit (GPU).

6. The processor of claim 1 , wherein the two or more computing resources include a first hardware component of a computer system and a second hardware component of the computer system, and the API is to select the one or more interconnects based, at least in part, on one or more function calls and one or more characteristics of the one or more interconnects.

7. The processor of claim 1 , wherein the API is to identify a set of available block devices, and select the one or more interconnects based, at least in part, on the set of available block devices.

8. The processor of claim 1 , wherein the API is to cause the information to be transferred using a path that includes a buffer managed by an intermediate device.

9. A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:

Perform an application programming interface (API) to select one or more interconnects to be used to transfer information among two or more computing resources based, at least in part, on one or more performance metrics corresponding to the one or more interconnects.

10. The non-transitory machine-readable medium of claim 9 , wherein the API is to determine one or more transfer path characteristics, and cause the information to be transferred based, at least in part, on the one or more transfer path characteristics.

11. The non-transitory machine-readable medium of claim 9 , wherein the API is to cause the information to be transferred based, at least in part, on a direct memory access capability of a buffer.

12. The non-transitory machine-readable medium of claim 9 , wherein the API is to select the one or more interconnects from a set of interconnects that includes a first type of interconnect and a second type of interconnect different from the first type of interconnect.

13. The non-transitory machine-readable medium of claim 9 , wherein the API is to select the one or more interconnects from a set of interconnects that includes a peripheral component interconnect express (PCIe) interconnect and a graphics processing unit (GPU) to GPU interconnect.

14. The non-transitory machine-readable medium of claim 9 , wherein the API is to cause the information to be transferred using a path that includes a buffer managed by an intermediate device.

15. A method, comprising:

performing an application programming interface (API) to select one or more interconnects to be used to transfer information among two or more computing resources based, at least in part, on one or more performance metrics corresponding to the one or more interconnects.

16. The method of claim 15 , wherein the API is to cause the information to be transferred is based, at least in part, on a congestion level of a path over which the information is to be transferred.

17. The method of claim 15 , wherein the API is to select the one or more interconnects based, at least in part, on one or more function calls that specify one or more of a read operation and a write operation.

18. The method of claim 15 , wherein the API is to identify a plurality of values corresponding to a plurality of dynamic component conditions, and determine a path over which the information is to be transferred based, at least in part, on the plurality of values.

19. The method of claim 15 , wherein the API is to identify a set of available block devices, and select the one or more interconnects based, at least in part, on the set of available block devices.

20. The method of claim 15 , wherein the API is to select a graphics processing unit (GPU) according to one or more predetermined criteria, and cause the information to be transferred over a path that includes the selected GPU.

21. A system comprising:

one or more processors to perform an application programming interface (API) to select one or more interconnects to be used to transfer information among two or more computing resources based, at least in part, on one or more performance metrics corresponding to the one or more interconnects.

22. The system of claim 21 , wherein the API is to select the one or more interconnects from a set of interconnects that includes a first type of interconnect and a second type of interconnect different from the first type of interconnect.

23. The system of claim 21 , wherein the API is to select a hardware device according to one or more predetermined criteria, and cause the information to be transferred over a path that includes the selected hardware device.

24. The system of claim 21 , wherein the API is to cause the information to be transferred based, at least in part, on a predetermined cost function.

25. The system of claim 21 , wherein API is to cause the information to be transferred based, at least in part, on a congestion level of a link, wherein the link is not included in a path over which the information is to be transferred.

26. The system of claim 21 , wherein the API is to cause the information to be transferred using a path that includes a buffer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2021
From: MODUKURI, KIRAN KUMAR; NEWBURN, CHRISTOPHER J.; SEN, SAPTARSHI; JOSHI, SANDEEP; KAILASH, AKILESH
To: NVIDIA CORPORATION
Reel/Frame 057583/0719 →
Continuity (2)
Continuation 16816122 · Mar 11, 2020
Related Publication 20220012207A1 · Jan 13, 2022