IP Library › Granted Patent US 11,963,412
Granted Patent B2
US 11,963,412 · App. 17/844,849 · Granted Apr 16, 2024

Display device having first and second gates disposed on a first side of an active area and a pattern disposed on a second side of the active area

Inventors: Suyeon Yun (Seoul, KR); Sunghoon Kim (Seoul, KR); Anna Ryu (Hwaseong-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H10K59/131G09G3/3266G09G3/3275H10K59/1213H10K59/1216
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Quick Facts
Patent No.
US 11,963,412
App. No.
17/844,849
Granted
Apr 16, 2024
Kind
B2
Abstract

A display device including: a panel including pixels, a pixel including; an LED; a capacitor between a first voltage line and a node; a first transistor between the first voltage line and a first electrode of the LED; a second transistor between a data line and a source of the first transistor; a third transistor between the node and a drain of the first transistor; a fourth transistor between the node and a second voltage line; a fifth transistor between the first voltage line and the source of the first transistor; a sixth transistor between the first electrode and the drain of the first transistor; and a seventh transistor between the second voltage line and the first electrode, the third and fourth transistor including: an active area including metal oxide; first and second gates above the active area; and a pattern below the active area.

Claims (20)

1. A display device, comprising:

a display panel comprising a pixel, the pixel comprising:

a light emitting diode;

a capacitor connected between a first voltage line and a reference node;

a first transistor connected between the first voltage line and a first electrode of the light emitting diode;

a second transistor connected between a data line and a source of the first transistor;

a third transistor connected between the reference node and a drain of the first transistor;

a fourth transistor connected between the reference node and a second voltage line;

a fifth transistor connected between the first voltage line and the source of the first transistor;

a sixth transistor connected between the first electrode of the light emitting diode and the drain of the first transistor; and

a seventh transistor connected between the second voltage line and the first electrode of the light emitting diode, at least one of the third transistor and the fourth transistor comprising:

an active area comprising a metal oxide;

a gate disposed above the active area; and

a first pattern comprising polysilicon, disposed under the active area, and overlapping the active area when viewed in a plan view, wherein the first pattern of the fourth transistor extends from the first pattern of the third transistor.

2. The display device of claim 1 , wherein the first pattern of the third transistor extends from an active area of the first transistor.

3. The display device of claim 1 , wherein the active area of the fourth transistor extends from the active area of the third transistor.

4. The display device of claim 1 , wherein each of the third transistor and the fourth transistor further comprises a second pattern disposed between its active area and its first pattern.

5. The display device of claim 4 , wherein the second voltage line and the second pattern are disposed on a same layer and comprise a same metal.

6. The display device of claim 4 , wherein the second pattern of the third transistor at least overlaps the first pattern of the third transistor when viewed in the plan view.

7. The display device of claim 1 , wherein each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor and the fourth transistor is an N-type transistor.

Priority Claims (1)
KR 10-2019-0057994 · May 17, 2019 · national
Continuity (2)
Division 16875034 · May 15, 2020
Related Publication 20220320256A1 · Oct 6, 2022
Cited By (1)
US 12,389,773