Detrapping electrons to prevent quick charge loss during program verify operations in a memory device
Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a multi-pass program operation on the memory array, the multi-pass program operation comprising a plurality of program phases and a plurality of program verify phases; and
causing a negative voltage signal to be applied to a first selected word line of a block of the memory array and to a second word line adjacent to the first selected word line during a first program verify phase of the plurality of program verify phases, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the multi-pass program operation.
2. The memory device of claim 1 , wherein the negative voltage signal is applied to the first selected word line before a positive pass voltage signal is applied to the first selected word line during the first program verify phase of the plurality of program verify phases.
3. The memory device of claim 1 , wherein the second word line is coupled to a second memory cell of the first plurality of memory cells on a first side of the first memory cell in the string of memory cells.
4. The memory device of claim 3 , wherein the control logic to perform operations further comprising:
causing the negative voltage signal to be applied to the first selected word line and to a third word line adjacent to the first selected word line during a second program verify phase of the plurality of program verify phases.
5. The memory device of claim 4 , wherein the third word line is coupled to a third memory cell of the first plurality of memory cells on a second side of the first memory cell in the string of memory cells.
6. The memory device of claim 1 , wherein the negative voltage signal is applied to the selected word line after a positive pass voltage signal and one or more program verify voltage signals are applied to the selected word line during the first program verify phase of the plurality of program verify phases.
7. The memory device of claim 1 , wherein each of the plurality of program phases and the plurality of program verify phases are associated with different programming voltages, and wherein the negative voltage is applied to the first selected word line only during a subset of the plurality of program verify phases associated with programming voltages that exceed a predefined threshold voltage level.
8. A method comprising:
initiating a multi-pass program operation on a memory array of a memory device, the multi-pass program operation comprising a plurality of program phases and a plurality of program verify phases; and
causing a negative voltage signal to be applied to a first selected word line of a block of the memory array and to a second word line adjacent to the first selected word line during a first program verify phase of the plurality of program verify phases, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the multi-pass program operation.
9. The method of claim 8 , wherein the negative voltage signal is applied to the first selected word line before a positive pass voltage signal is applied to the first selected word line during the first program verify phase of the plurality of program verify phases.
10. The method of claim 8 , wherein the second word line is coupled to a second memory cell of the first plurality of memory cells on a first side of the first memory cell in the string of memory cells.
11. The method of claim 10 , further comprising:
causing the negative voltage signal to be applied to the first selected word line and to a third word line adjacent to the first selected word line during a second program verify phase of the plurality of program verify phases.
12. The method of claim 11 , wherein the third word line is coupled to a third memory cell of the first plurality of memory cells on a second side of the first memory cell in the string of memory cells.
13. The method of claim 8 , wherein the negative voltage signal is applied to the selected word line after a positive pass voltage signal and one or more program verify voltage signals are applied to the selected word line during the first program verify phase of the plurality of program verify phases.
14. The method of claim 8 , wherein each of the plurality of program phases and the plurality of program verify phases are associated with different programming voltages, and wherein the negative voltage is applied to the first selected word line only during a subset of the plurality of program verify phases associated with programming voltages that exceed a predefined threshold voltage level.