Resistive random access memory device with three-dimensional cross-point structure and method of operating the same
A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.
1. A memory device, comprising:
a substrate;
a first wiring layer extending in a first direction parallel to the substrate;
a second wiring layer extending in a second direction crossing the first direction, the second direction being parallel to the substrate;
a third wiring layer being adjacent to the second wiring layer in a third direction, the third wiring layer extending in the second direction, the third direction perpendicular to the first direction and the second direction;
a fourth wiring layer extending in the first direction, the third wiring layer being provided between the second wiring layer and the fourth wiring layer;
a first resistance changing layer connected between the first wiring layer and the second wiring layer;
a second resistance changing layer connected between the third wiring layer and the fourth wiring layer;
a first insulating layer adjacent to the first resistance changing layer in the second direction; and
a second insulating layer adjacent to the first resistance changing layer in the second direction via the first insulating layer, the first insulating layer being located between the first resistance changing layer and the second insulating layer in the second direction,
wherein the first resistance changing layer includes indium.
2. The memory device according to claim 1 , wherein the first insulating layer include silicon and nitrogen.
3. The memory device according to claim 1 , further comprising:
a first layer provided on the first wiring layer.
4. The memory device according to claim 3 , wherein the first layer include tungsten and nitrogen.
5. The memory device according to claim 1 , further comprising:
a circuit being provided on the substrate.
6. The memory device according to claim 5 , wherein the circuit provided below the first resistance changing layer in the third direction.
7. The memory device according to claim 1 , further comprising:
a second layer being provided on the third wiring layer.
8. The memory device according to claim 7 , wherein the second layer include tungsten and nitrogen.
9. The memory device according to claim 1 , further comprising:
a third insulating layer being provided between the second wiring layer and the third wiring layer.
10. The memory device according to claim 1 , wherein the second resistance changing layer includes indium.
11. The memory device according to claim 1 , wherein a variable resistance changing layer is not provided between the second wiring layer and the third wiring layer.
12. The memory device according to claim 1 , wherein the first resistance changing layer is directly connected to the first insulating layer.