Method of forming semiconductor package transmission lines with micro-bump lines

1. A method comprising:

forming a first insulator layer over a first substrate;

forming a redistribution layer over the first insulator layer, the redistribution layer comprising a first redistribution line and a second redistribution line;

forming a second insulator layer over the redistribution layer;

forming a micro-bump layer over the second insulator layer, forming the micro-bump layer comprising simultaneously forming a micro-bump line and a micro-bump structure, wherein the micro-bump line is laterally above the first redistribution line and the micro-bump structure contacts the second redistribution line, wherein the micro-bump line and the micro-bump structure comprise a same one or more layers, wherein the micro-bump line and the micro-bump structure each comprise a layer of solder material, wherein the micro-bump line is a signal transmission line coupled to transmit a signal horizontally over a surface of the second insulator layer;

attaching a second substrate to the micro-bump structure; and

forming an underfill interposed between the second insulator layer and the second substrate, the underfill completely separating the micro-bump line and the second substrate.

2. The method of claim 1 , wherein the redistribution layer comprises a plurality of slots.

3. The method of claim 1 , wherein the micro-bump line extends laterally past opposing sidewalls of the first redistribution line in a cross-sectional view.

4. The method of claim 1 , wherein the first redistribution line extends laterally past opposing sidewalls of the micro-bump line in a cross-sectional view, wherein the opposing sidewalls of the micro-bump line are at a widest width of the micro-bump line in the cross-sectional view.

5. The method of claim 1 , wherein the first redistribution line and the micro-bump line form a transmission line.

6. The method of claim 5 , wherein the first redistribution line is a ground plane.

7. The method of claim 1 , further comprising a first under bump metal (UBM) line and a second UBM line, wherein the first UBM line is interposed between the micro-bump line and the second insulator layer, wherein the second UBM line electrically couples the micro-bump structure to the second redistribution line.

8. The method of claim 1 , further comprising a plurality of through vias extending through the first substrate.

9. A method comprising:

forming a first insulator layer over a first substrate, the first substrate having a redistribution line;

forming a micro-bump layer over the first insulator layer, the micro-bump layer comprising a first micro-bump line and a micro-bump structure, wherein the first insulator layer is interposed between the redistribution line and the first micro-bump line, each of the first micro-bump line and the micro-bump structure comprising one or more metallic layers and a solder layer on the one or more metallic layers, wherein the one or more metallic layers is interposed between the solder layer and the first insulator layer;

bonding a second substrate to the micro-bump structure by the solder layer of the micro-bump structure; and

placing an underfill between the first micro-bump line and the second substrate, the underfill completely separating the first micro-bump line and the second substrate.

10. The method of claim 9 , wherein forming the micro-bump layer further comprises:

forming a first via and a second via to the redistribution line; and

forming a second micro-bump line coupled to the first via and forming a third micro-bump line coupled to the second via, wherein the first micro-bump line is interposed between the second micro-bump line and the third micro-bump line.

11. The method of claim 9 , further comprising forming the redistribution line, wherein the redistribution line comprises a plurality of slots.

12. The method of claim 9 , wherein the first micro-bump line comprises a first layer, a second layer and a third layer, wherein a ratio of heights for the first layer/the second layer/the third layer is 15/1.5/10.

13. The method of claim 9 , wherein a narrower one of the first micro-bump line and the redistribution line is a signal transmission line and a wider one of the first micro-bump line and the redistribution line is a ground plane, wherein a width of the ground plane is 1.5 times to 2 times a width of the signal transmission line.

14. The method of claim 9 , wherein the first insulator layer completely covers a lower surface of the first micro-bump line.

15. A method comprising:

forming a redistribution line on a first substrate;

a first insulator layer over the redistribution line;

forming one or more micro-bump lines over the first insulator layer;

forming a micro-bump structure, wherein each of the one or more micro-bump lines and the micro-bump structure have a same conductive layer structure, wherein the conductive layer structure of both the one or more micro-bump lines and the micro-bump structure comprises a solder layer and one or more metal layers between the solder layer and the first insulator layer, wherein the one or more micro-bump lines are electrically coupled to ground or a signal line;

attaching a second substrate to the micro-bump structure by the solder layer of the micro-bump structure; and

placing an underfill between the one or more micro-bump lines and the second substrate, wherein the underfill extends closer to the second substrate than the one or more micro-bump lines.

16. The method of claim 15 , wherein the one or more micro-bump lines comprises a first micro-bump line, a second micro-bump line, and a third micro-bump line, wherein the first micro-bump line is interposed between the second micro-bump line and the third micro-bump line, wherein the second micro-bump line and the third micro-bump line are electrically coupled to the redistribution line.

17. The method of claim 15 , wherein the first substrate is part of an interposer.

18. The method of claim 15 , wherein the first substrate is part of an integrated circuit die.

19. The method of claim 15 , wherein the first insulator layer has a thickness between 5 μm and 30 μm.

20. The method of claim 15 , wherein a height of the micro-bump structure is between 10 μm to 50 μm.