Semiconductor device and method

1. A device comprising:

a first fin;

a gate structure over the first fin;

a first source/drain region adjacent the gate structure and in the first fin;

a dielectric material over the first source/drain region; and

a conductive line over the dielectric material, the conductive line isolated from the first source/drain region by the dielectric material, a top surface of the conductive line being coplanar with a top surface of the gate structure.

2. The device of claim 1 further comprising:

a second source/drain region adjacent the gate structure, the dielectric material disposed over the second source/drain region; and

a source/drain contact extending through the dielectric material, the source/drain contact connected to the second source/drain region, a top surface of the source/drain contact being coplanar with the top surface of the conductive line and the top surface of the gate structure.

3. The device of claim 2 further comprising:

an interconnect structure comprising conductive features interconnecting the conductive line, the source/drain contact, and the gate structure.

4. The device of claim 2 , wherein the conductive line has a first portion and a second portion, the first portion disposed over the first source/drain region, the second portion disposed adjacent the first source/drain region, the first portion having a first height, the second portion having a second height, the first height less than the second height.

5. The device of claim 2 , wherein the conductive line has a first length, the source/drain contact has a second length, and the first length is greater than the second length, each of the first length and the second length measured in a direction that is parallel to a longitudinal axis of the gate structure.

6. The device of claim 2 , wherein the conductive line has a first width and the source/drain contact has the first width, the first width measured in a direction that is parallel to a longitudinal axis of the first fin.

7. The device of claim 1 further comprising:

a second fin, the gate structure over the second fin; and

a second source/drain region adjacent the gate structure and in the second fin, the dielectric material disposed over the second source/drain region, the conductive line extending across the first source/drain region and the second source/drain region.

8. The device of claim 1 further comprising:

a source/drain contact extending through the first fin, the source/drain contact connected to the first source/drain region.

9. A device comprising:

a back-side interconnect structure comprising a power rail;

a front-side interconnect structure comprising interconnects; and

a device layer between the back-side interconnect structure and the front-side interconnect structure, the device layer comprising:

a transistor comprising a first source/drain region and a second source/drain region;

a source/drain contact contacting a front-side of the first source/drain region, the interconnects connected to the source/drain contact;

a power rail contact contacting a back-side of the second source/drain region, the power rail connected to the power rail contact;

a dielectric material completely covering a front-side of the second source/drain region; and

a conductive line on the dielectric material, the interconnects connected to the conductive line.

10. The device of claim 9 , wherein the conductive line and the source/drain contact have a same width in a first direction, and the conductive line has a greater length than the source/drain contact in a second direction, the second direction perpendicular to the first direction.

11. The device of claim 9 , wherein the interconnects comprise a first level conductive line, a width of the power rail being greater than a width of the first level conductive line.

12. The device of claim 11 , wherein the width of the power rail is at least twice the width of the first level conductive line.

13. The device of claim 9 , wherein a surface of the conductive line is coplanar with a surface of the source/drain contact.

14. The device of claim 9 , wherein the interconnects of the front-side interconnect structure are electrically connected to the first source/drain region to form a logic circuit, the back-side interconnect structure further comprises an embedded passive device, and the embedded passive device is integrated with the power rail to form a power circuit.

15. A method comprising:

depositing an etch stop layer on a first source/drain region of a transistor and on a second source/drain region of the transistor;

depositing an interlayer dielectric on the etch stop layer;

forming a source/drain contact through the interlayer dielectric and the etch stop layer, the source/drain contact contacting a front-side of the first source/drain region; and

forming a conductive line through the interlayer dielectric, the etch stop layer completely separating the conductive line from a front-side of the second source/drain region.

16. The method of claim 15 , wherein the conductive line is formed after the source/drain contact is formed.

17. The method of claim 15 , wherein forming the source/drain contact comprises etching a first opening through the interlayer dielectric and the etch stop layer with a first etching process, forming the conductive line comprises etching a second opening through the interlayer dielectric with a second etching process, and the second etching process is different from the first etching process.

18. The method of claim 17 , wherein etching the first opening comprises:

patterning a mask for the first etching process over the interlayer dielectric, the mask having a pattern of openings over the first source/drain region and the second source/drain region; and

covering a portion of the pattern of openings over the second source/drain region.

19. The method of claim 17 , wherein etching the first opening comprises:

patterning a mask for the first etching process over the interlayer dielectric, the mask having a pattern of openings over the first source/drain region but not over the second source/drain region.

20. The method of claim 15 further comprising:

planarizing the conductive line and the source/drain contact so that a top surface of the conductive line is coplanar with a top surface of the source/drain contact.