Semiconductor devices
In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.
1. A device comprising:
a first nanostructure;
a gate structure wrapped around the first nanostructure;
a first source/drain region adjacent the gate structure;
a first dielectric layer over the first source/drain region;
an interlayer dielectric over the first dielectric layer, a material of the interlayer dielectric being different than a material of the first dielectric layer; and
a conductive line extending through the interlayer dielectric, the conductive line disposed over the first source/drain region, the conductive line isolated from the first source/drain region by the first dielectric layer, a top surface of the conductive line being coplanar with a top surface of the gate structure.
2. The device of claim 1 , further comprising:
a second nanostructure; and
a second source/drain region adjacent the second nanostructure, the first dielectric layer disposed over the second source/drain region, the conductive line extending across the first source/drain region and the second source/drain region in a top-down view.
3. The device of claim 2 , wherein the conductive line has a first length as it extends across the first source/drain region and the second source/drain region in the top-down view, the conductive line has a first width in the top-down view, and the first length is greater than the first width.
4. The device of claim 1 , further comprising:
a second source/drain region adjacent the gate structure on an opposite side from the first source/drain region, the first dielectric layer disposed over the second source/drain region; and
a source/drain contact extending through the interlayer dielectric and the first dielectric layer, the source/drain contact connected to the second source/drain region.
5. The device of claim 4 , wherein the source/drain contact and the conductive line have a same width.
6. The device of claim 1 , further comprising:
a second dielectric layer under the first source/drain region; and
a power rail contact extending through the second dielectric layer, the power rail contact connected to the first source/drain region.
7. The device of claim 1 , further comprising:
dielectric layers over the gate structure and the conductive line; and
interconnects in the dielectric layers, the interconnects connected to the conductive line and the gate structure.
8. A device comprising:
a back-side interconnect structure comprising a power rail;
a front-side interconnect structure comprising a first interconnect; and
a device layer between the back-side interconnect structure and the front-side interconnect structure, the device layer comprising:
a transistor comprising a source/drain region;
a power rail contact contacting a back-side of the source/drain region, the power rail connected to the power rail contact;
a dielectric material completely covering a front-side of the source/drain region; and
a conductive line on the dielectric material, the first interconnect connected to the conductive line.
9. The device of claim 8 , wherein the front-side interconnect structure further comprises a second interconnect, the second interconnect connected to the conductive line.
10. The device of claim 8 , wherein a width of the power rail is greater than a width of the first interconnect.
11. The device of claim 10 , wherein the first interconnect is a first level conductive line of the front-side interconnect structure.
12. The device of claim 8 , wherein the transistor further comprises a gate structure and a surface of the conductive line is coplanar with a surface of the gate structure.
13. The device of claim 8 , wherein the back-side interconnect structure further comprises a passive device, the power rail connected to the passive device.
14. The device of claim 8 , further comprising:
a support substrate attached to the front-side interconnect structure; and
an external connector connected to the power rail.
15. A device comprising:
a first dielectric layer;
a nanostructure over the first dielectric layer;
a gate structure wrapped around the nanostructure;
a first spacer adjacent the gate structure;
a first source/drain region adjacent the first spacer and the nanostructure;
a second dielectric layer completely covering a front-side of the first source/drain region; and
a power rail contact extending through the first dielectric layer, the power rail contact connected to a back-side of the first source/drain region.
16. The device of claim 15 , further comprising:
a fin between the first dielectric layer and the nanostructure, the power rail contact extending through the fin.
17. The device of claim 15 , further comprising:
a second spacer adjacent the gate structure on an opposite side from the first spacer;
a second source/drain region adjacent the second spacer and the nanostructure, the second dielectric layer disposed over a front-side of the second source/drain region; and
a source/drain contact extending through the second dielectric layer, the source/drain contact connected to the front-side of the second source/drain region.
18. The device of claim 17 , wherein a surface of the source/drain contact is coplanar with a surface of the gate structure.
19. The device of claim 18 , wherein the surface of the gate structure is coplanar with a surface of the first spacer and a surface of the second spacer.
20. The device of claim 15 , further comprising:
a conductive line on the second dielectric layer.