Isolation structures of semiconductor devices
The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.
1. A method, comprising:
forming a vertical structure comprising a fin base on a substrate and a stack of first and second nanostructured layers on the fin base;
forming polysilicon gate structures on first portions of the vertical structure;
forming doped layers with dopants of a first type conductivity on second portions of the vertical structure;
doping one of the polysilicon gate structures with dopants of a second type conductivity; and
replacing at least two of the polysilicon gate structures adjacent to the one of the polysilicon gate structures with high-k metal gate structures.
2. The method of claim 1 , wherein doping the one of the polysilicon gate structures comprises ion implanting the dopants of the second type conductivity into the one of the polysilicon gate structures.
3. The method of claim 1 , wherein the one of the polysilicon gate structures is interposed between the at least two of the polysilicon gate structures.
4. The method of claim 1 , further comprising patterning a photoresist layer on the at least two of the polysilicon gate structures prior to doping the one of the polysilicon gate structures.
5. The method of claim 1 , wherein replacing the at least two of the polysilicon gate structures comprises:
patterning a photoresist layer on the one of the polysilicon gate structures after doping the one of the polysilicon gate structures; and
etching the at least two of the polysilicon gate structures.
6. The method of claim 1 , wherein a work function value of the one of the polysilicon gate structures is greater than a work function value of the high-k metal gate structures.
7. The method of claim 1 , wherein forming the polysilicon gate structures comprises forming the polysilicon gate structures with an aspect ratio equal to or greater than 9.
8. The method of claim 1 , further comprising:
depositing an oxide layer on the first and second portions of the vertical structure;
forming the polysilicon gate structures on first portions of the oxide layer; and
removing second portions of the oxide layer to expose the second portions of the vertical structure prior to forming the doped layers.
9. The method of claim 1 , wherein forming the doped layers comprises epitaxially growing a semiconductor material on the second portions of the vertical structure.
10. The method of claim 1 , wherein forming the doped layers comprises epitaxially growing a semiconductor material on sidewalls of the first and second nanostructured layers.
11. A method, comprising:
forming a vertical structure comprising a fin base on a substrate and a stack of first and second nanostructured layers on the fin base;
forming first and second polysilicon structures on first portions of the vertical structure;
forming doped regions with dopants of a first type conductivity on second portions of the vertical structure;
doping the first polysilicon structure with dopants of a second type conductivity; and
replacing the second polysilicon structure and portions of the vertical structure with metal gate structures.
12. The method of claim 11 , wherein forming the doped regions comprises epitaxially growing a semiconductor layer on sidewalls of the vertical structure.
13. The method of claim 11 , wherein forming the doped regions comprises replacing the first and second nanostructured layers in the second portions of the vertical structure with the doped regions.
14. The method of claim 11 , wherein replacing the second polysilicon structure and portions of the vertical structure with the metal gate structures comprises etching the second polysilicon structure and the second nanostructured layers.
15. The method of claim 11 , further comprising forming a masking layer on the first polysilicon structure prior to replacing the second polysilicon structure and portions of the vertical structure with the metal gate structures.
16. The method of claim 11 , wherein doping the first polysilicon structure comprises ion implanting the dopants of the second type conductivity into the first polysilicon structure.
17. A method, comprising:
forming first and second polysilicon structures on first portions of a substrate;
forming doped regions with dopants of a first type conductivity on second portions of the substrate;
doping the first polysilicon structure with dopants of a second type conductivity; and
replacing the second polysilicon structure with a metal gate structure.
18. The method of claim 17 , wherein forming the doped regions comprises epitaxially growing a semiconductor layer on the second portions of the substrate.
19. The method of claim 17 , further comprising forming a stack of first and second nanostructured layers on the substrate prior to forming the first and second polysilicon structures.
20. The method of claim 19 , wherein replacing the second polysilicon structure comprises etching the second nanostructured layers.