Semiconductor device with source/drain epitaxial layer
A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.
1. A semiconductor device comprises:
a plurality of gate electrodes over a substrate;
a source/drain epitaxial layer disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes;
a silicide region on the source/drain epitaxial layer;
a plurality of lightly doped drains located in the substrate to be electrically connected to the source/drain epitaxial layer, wherein the plurality of lightly doped drains comprise first portions, and the first portions protrude from sidewalls of the source/drain epitaxial layer and covered by the silicide region; and
a plurality of pocket regions located in the substrate and below the plurality of lightly doped drains.
2. The semiconductor device according to claim 1 , wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to the depth of one-half to two-thirds of the spacing between the two adjacent gate electrodes.
3. The semiconductor device according to claim 1 , wherein the source/drain epitaxial layer comprises a SiGe structure.
4. The semiconductor device according to claim 1 , wherein a maximum width of the source/drain epitaxial layer is less than twice the spacing between the two adjacent gate electrodes.
5. The semiconductor device according to claim 1 , further comprising:
a plurality of spacers on sidewalls of the plurality of gate electrodes.
6. The semiconductor device according to claim 5 , wherein:
the plurality of lightly doped drains comprise second portions, and the second portions are located below the plurality of spacers.
7. The semiconductor device according to claim 1 , wherein the plurality of pocket regions located between the plurality of lightly doped drains and the source/drain epitaxial layer.
8. The semiconductor device according to claim 5 , wherein:
the silicide region on the source/drain epitaxial layer is located between the plurality of spacers.
9. The semiconductor device according to claim 8 , wherein the silicide region is in contact with source/drain epitaxial layer and the first portions of the plurality of lightly doped drains.
10. A semiconductor device comprises:
a substrate;
a plurality of gate electrodes disposed on the substrate;
a SiGe structure disposed in the substrate and between two adjacent gate electrodes, wherein a distance from a bottom surface of the SiGe structure to a top surface of the substrate is in a range from one-half to two-thirds of a spacing between the two adjacent gate electrodes;
a silicide region on SiGe structure;
a plurality of lightly doped drains located in the substrate, wherein the plurality of lightly doped drains comprise first portions, and the first portions are not overlap with the SiGe structure and covered by the silicide region; and
a plurality of pocket regions located in the substrate and below the plurality of lightly doped drains.
11. The semiconductor device according to claim 10 , wherein a maximum width of the SiGe structure is less than twice the spacing between the two adjacent gate electrodes.
12. The semiconductor device according to claim 10 , further comprising:
a plurality of dielectric layers over the top surface of the substrate; and
a plurality of interfacial layers between the plurality of dielectric layers and the substrate.
13. The semiconductor device according to claim 12 , wherein the plurality of gate electrodes comprise:
a plurality of metal layers; and
a plurality of work function metal layers sandwiched between the plurality of dielectric layers and the plurality of metal layers and surrounding sidewalls of the plurality of metal layers.
14. The semiconductor device according to claim 13 , wherein the distance from the bottom surface of the SiGe structure to the top surface of the substrate is in a range from one-half to two-thirds of the spacing between two adjacent work function metal layers of the two adjacent gate electrodes.
15. A semiconductor device comprises:
a semiconductor substrate;
a plurality of dielectric layers over the substrate;
a plurality of interfacial layers between the plurality of dielectric layers and the substrate;
a plurality of gate electrodes disposed over the plurality of dielectric layers comprising:
a plurality of metal layers; and
a plurality of work function metal layers surrounding bottoms and sidewalls of the plurality of metal layers; and
a source/drain epitaxial layer disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent work function metal layers;
a silicide region on the top surface of the source/drain epitaxial layer; and
a plurality of lightly doped drains located in the substrate to be electrically connected to the source/drain epitaxial layer, wherein the plurality of lightly doped drains comprise first portions, and the first portions protrude from sidewalls of the source/drain epitaxial layer and covered by the silicide region,
wherein the silicide region is in contact with the top surface of the source/drain epitaxial layer and top surfaces of the first portions of the plurality of lightly doped drains.
16. The semiconductor device according to claim 15 , wherein a maximum width of the source/drain epitaxial layer is less than twice the spacing between the two adjacent work function metal layers.
17. The semiconductor device according to claim 15 , further comprising:
a plurality of spacers on sidewalls of the plurality of gate electrodes; and
wherein the plurality of lightly doped drains comprise second portions, and the second portions are located below the plurality of spacers.
18. The semiconductor device according to claim 17 , wherein a top surface of the source/drain epitaxial layer is higher than top surfaces of the plurality of lightly doped drains.
19. The semiconductor device according to claim 15 , further comprising:
a plurality of pocket regions located in the substrate and below the plurality of lightly doped drains.
20. The semiconductor device according to claim 19 , wherein the plurality of pocket regions located between the plurality of lightly doped drains and the source/drain epitaxial layer.