Semiconductor packages having first and second redistribution patterns
A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.
1. A semiconductor package, comprising:
a redistribution substrate including first and second redistribution patterns that have respective bottom surfaces that are at different distances from a bottom surface of the redistribution substrate in a vertical direction that is perpendicular to the bottom surface of the redistribution substrate; and
a semiconductor chip on the redistribution substrate, the semiconductor chip including a plurality of chip pads electrically connected to the first and second redistribution patterns,
wherein the first redistribution pattern includes
a first metal pattern on a first dielectric layer, and
a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern,
wherein the second redistribution pattern includes
a second metal pattern in a second dielectric layer, and
a second barrier pattern that is
between the second dielectric layer and a bottom surface of the second metal pattern, and
between the second dielectric layer and a sidewall of the second metal pattern, and
wherein the second dielectric layer is on the first dielectric layer and directly contacts a sidewall of the first metal pattern.
2. The semiconductor package of claim 1 , wherein a top surface of the second dielectric layer is at a same distance from the bottom surface of the redistribution substrate in the vertical direction as a top surface of the second redistribution pattern.
3. The semiconductor package of claim 1 , wherein
the sidewall of the first metal pattern is misaligned with a sidewall of the first barrier pattern such that the sidewall of the first metal pattern is offset from the sidewall of the first barrier pattern in a horizontal direction that is parallel to the bottom surface of the redistribution substrate, and
a portion of the second dielectric layer is between the bottom surface of the first metal pattern and a top surface of the first dielectric layer.
4. The semiconductor package of claim 1 , wherein
the first redistribution pattern has a first minimum width in a horizontal direction that is parallel to the bottom surface of the redistribution substrate,
the second redistribution pattern has a second minimum width in the horizontal direction, and
the second minimum width is smaller in magnitude than the first minimum width.
5. The semiconductor package of claim 1 , wherein the second redistribution pattern includes
a via part that penetrates a portion of the second dielectric layer;
a pad part in the second dielectric layer and connected to the via part; and
a line part in the second dielectric layer and extending away from the pad part,
wherein the pad part has a first thickness in the vertical direction, and
wherein the line part has a second thickness in the vertical direction that is smaller in magnitude than the first thickness.
6. The semiconductor package of claim 5 , wherein
a top surface of the line part is at a same distance from the bottom surface of the redistribution substrate in the vertical direction as a top surface of the pad part, and
a bottom surface of the line part is at a different distance from the bottom surface of the redistribution substrate in the vertical direction than a bottom surface of the pad part.
7. The semiconductor package of claim 5 , wherein the second redistribution pattern has a rounded edge between a sidewall of the via part and a bottom surface of the pad part.
8. The semiconductor package of claim 1 , wherein
the first metal pattern has a linear sidewall, and
the second metal pattern has a rounded sidewall.
9. The semiconductor package of claim 1 , wherein the second metal pattern has
a minimum width at a top surface of the second metal pattern or the bottom surface of the second metal pattern, and
a maximum width at a level that is between the top surface of the second metal pattern and the bottom surface of the second metal pattern.
10. The semiconductor package of claim 1 , wherein the second redistribution pattern includes
a via part that penetrates a portion of the second dielectric layer;
a pad part in the second dielectric layer and connected to the via part; and
a line part in the second dielectric layer and extending away from the pad part,
wherein the line part of the second redistribution pattern has a width of about 0.5 μm to about 2.5 μm.
11. A semiconductor package, comprising:
a redistribution substrate that includes a plurality of first redistribution layers and a plurality of second redistribution layers that are vertically and alternately stacked in a vertical direction that is perpendicular to a bottom surface of the redistribution substrate; and
a semiconductor chip on the redistribution substrate,
wherein each of the first redistribution layers includes
a first dielectric layer, and
a first redistribution pattern that includes a first via part and a first pad part connected to the first via part, the first via part penetrating the first dielectric layer, and the first pad part being on a top surface of the first dielectric layer,
wherein each of the second redistribution layers includes
a second dielectric layer on an underlying first dielectric layer of an underlying first redistribution layer, and
a second redistribution pattern that includes a second via part and a second pad part connected to the second via part, the second via part penetrating a portion of the second dielectric layer, and the second pad part is in the second dielectric layer,
wherein the first redistribution pattern includes
a first metal pattern on a first dielectric layer, and
a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern,
wherein the second redistribution pattern includes
a second metal pattern in a second dielectric layer, and
a second barrier pattern that is
between the second dielectric layer and a bottom surface of the second metal pattern, and
between the second dielectric layer and a sidewall of the second metal pattern, and
wherein the second dielectric layer is on the first dielectric layer and directly contacts a sidewall of the first metal pattern.
12. The semiconductor package of claim 11 , wherein
the second dielectric layer covers a sidewall of an underlying first redistribution pattern of the underlying first redistribution layer, and
a top surface of the second dielectric layer is coplanar with a top surface of the second redistribution pattern.
13. The semiconductor package of claim 11 , wherein
the first pad part of the first redistribution pattern has a linear sidewall, and
the second pad part of the second redistribution pattern has a rounded sidewall.
14. The semiconductor package of claim 11 , wherein
the second redistribution pattern further includes a line part in the second dielectric layer and extending away from the second pad part, and
the line part of the second redistribution pattern has
a minimum width at a top surface of the line part or a bottom surface of the line part, and
a maximum width at a level that is between the top surface of the line part and the bottom surface of the line part.
15. The semiconductor package of claim 14 , wherein each of the second pad part and the line part has a rounded sidewall.
16. The semiconductor package of claim 11 , wherein
the second redistribution pattern further includes a line part in the second dielectric layer and extending away from the second pad part,
a top surface of the line part of the second redistribution pattern is at a same distance from the bottom surface of the redistribution substrate in the vertical direction as a top surface of the second pad part of the second redistribution pattern, and
a bottom surface of the line part of the second redistribution pattern is at a different distance from the bottom surface of the redistribution substrate in the vertical direction than a bottom surface of the second pad part of the second redistribution pattern.
17. The semiconductor package of claim 11 , wherein the first redistribution pattern further includes a first line part on the top surface of the first dielectric layer and extending away from the first pad part,
the second redistribution pattern further includes a second line part in the second dielectric layer and extending away from the second pad part,
the first line part of the first redistribution pattern has a first minimum width,
the second line part of the second redistribution pattern has a second minimum width, and
the second minimum width is smaller in magnitude than the first minimum width.
18. A semiconductor package, comprising:
a lower redistribution substrate that includes a first redistribution pattern on a first dielectric layer and a second redistribution pattern in a second dielectric layer on the first dielectric layer;
a first semiconductor chip on the lower redistribution substrate, the first semiconductor chip including a plurality of chip pads;
a plurality of first connection terminals between the lower redistribution substrate and the plurality of chip pads of the first semiconductor chip;
a molding layer on the lower redistribution substrate, the molding layer covering the first semiconductor chip; and
a plurality of metal pillars around the first semiconductor chip and connected to the lower redistribution substrate, the metal pillars penetrating the molding layer,
wherein the second dielectric layer covers a sidewall of the first redistribution pattern,
wherein a top surface of the second dielectric layer is coplanar with a top surface of the second redistribution pattern,
wherein the first redistribution pattern includes
a first metal pattern on a first dielectric layer, and
a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern,
wherein the second redistribution pattern includes
a second metal pattern in a second dielectric layer, and
a second barrier pattern that is
between the second dielectric layer and a bottom surface of the second metal pattern, and
between the second dielectric layer and a sidewall of the second metal pattern, and
wherein the second dielectric layer is on the first dielectric layer and directly contacts a sidewall of the first metal pattern.