Chiplet interposer

1. A method comprising:

depositing a first dielectric fill over a first carrier substrate;

forming one or more metallization patterns over the first dielectric fill to form an interposer structure;

separating a first interposer and a second interposer from the interposer structure;

laterally encapsulating the first interposer in a first encapsulant;

after encapsulating the first interposer, forming a first redistribution structure over the first interposer;

attaching a first device to the first redistribution structure, wherein the first redistribution structure is between the first device and the first interposer;

after attaching the first device, laterally encapsulating the first device in a second encapsulant;

after encapsulating the first device, removing portions of the first encapsulant and removing the first carrier substrate of the first interposer to expose the first dielectric fill; and

forming external connectors on a side of the first interposer opposite the first redistribution structure, one or more of the external connectors electrically coupled to the first device by way of the first interposer.

2. The method of claim 1 , further comprising:

forming through vias extending through the first dielectric fill of the first interposer.

3. The method of claim 1 , further comprising:

forming through vias extending through the first encapsulant.

4. The method of claim 1 , further comprising:

forming a second redistribution structure over the first interposer, the second redistribution structure being wider than the first interposer, the second redistribution structure interposed between the first interposer and the external connectors.

5. The method of claim 1 , further comprising:

exposing a first section of a first photopatternable material to a first light mask pattern;

exposing a second section of the first photopatternable material to a second light mask pattern, the first section overlapping the second section, the first section and second section together forming a first pattern; and

forming a metallization pattern based on the first pattern.

6. The method of claim 5 , wherein the metallization pattern in an overlapping area of the first section and the second section has a wider line width than the metallization pattern in the first section or the second section.

7. The method of claim 1 , further comprising:

laterally encapsulating a third interposer, the third interposer adjacent the first interposer, the third interposer comprising a second dielectric fill formed on a second carrier substrate; and

removing the second carrier substrate to expose the second dielectric fill.

8. A method comprising:

singulating a first die from a first workpiece, the first workpiece comprising a semiconductor substrate, an insulating material fill over the semiconductor substrate, and a connector interface over the insulating material fill, wherein following singulating the first die, the insulating material fill has same lateral extents as the semiconductor substrate;

laterally encapsulating the first die in a first encapsulant;

after laterally encapsulating the first die in the first encapsulant, forming a first redistribution structure over the first die;

after forming the first redistribution structure over the first die, electrically coupling a second die to the first redistribution structure, the second die comprising a device die;

after electrically coupling the second die, laterally encapsulating the second die in a second encapsulant;

after laterally encapsulating the second die in the second encapsulant, grinding the first encapsulant and semiconductor substrate until the semiconductor substrate is removed; and

forming external connectors over the first die and over the first encapsulant.

9. The method of claim 8 , wherein the insulating material fill of the first die includes a set of through vias disposed in the insulating material fill.

10. The method of claim 8 , further comprising:

forming a second redistribution structure over the first die and over the first encapsulant, the second redistribution structure interposed between the first die and the external connectors.

11. The method of claim 8 , further comprising a through-via extending through the first encapsulant, wherein forming the external connectors comprises forming one of the external connectors directly on the through-via.

12. The method of claim 8 , further comprising:

patterning a first portion of a first metallization layer of the first die;

patterning a second portion of the first metallization layer of the first die, the first portion overlapping the second portion; and

forming a first conductor of the first metallization layer traversing from the first portion to the second portion, wherein a first width of the first conductor is greater where the first portion overlaps the second portion than a second width of the first conductor in either the first portion or the second portion alone.

13. The method of claim 12 , wherein the first conductor in the first portion is laterally offset the first conductor in the second portion.

14. A method comprising:

forming a first chiplet and a second chiplet, each of the first chiplet and the second chiplet comprising a stack of a silicon layer, an insulating layer, and a first redistribution structure, the first chiplet and the second chiplet being free of active devices;

attaching the first chiplet and the second chiplet to a carrier substrate, wherein the silicon layer is between the insulating layer and the carrier substrate;

after attaching the first chiplet and the second chiplet, encapsulating the first chiplet and the second chiplet with a first encapsulant;

after encapsulating the first chiplet and the second chiplet, forming a second redistribution structure over the first chiplet, the second chiplet, and the first encapsulant;

attaching a plurality of device dies to the second redistribution structure;

encapsulating the plurality of device dies with a second encapsulant;

after encapsulating the plurality of device dies, removing the carrier substrate; and

after removing the carrier substrate, completely removing the silicon layer of the first chiplet and the second chiplet.

15. The method of claim 14 , wherein forming the first chiplet and the second chiplet further comprises:

forming a stitched metallization pattern over the insulating layer, the stitched metallization pattern having a first portion, a second portion, and an overlapping portion corresponding to an overlapping area of the first portion and the second portion, wherein a first line width of the stitched metallization pattern in the first portion is less than a second line width of the stitched metallization pattern in the overlapping portion.

16. The method of claim 14 , further comprising:

after removing the silicon layer of the first chiplet and the second chiplet, forming a third redistribution structure, the first chiplet being between the third redistribution structure and the second redistribution structure.

17. The method of claim 14 , further comprising:

forming through vias over the carrier substrate, wherein encapsulating the first chiplet and the second chiplet comprises encapsulating the through vias.

18. The method of claim 14 , further comprising, prior to attaching the plurality of device dies:

encapsulating the second redistribution structure with a third encapsulant.

19. The method of claim 18 , wherein at least a first device die of the plurality of device dies overlap the first chiplet and the second chiplet.