Adaptive semi-circle select gate bias

1. A memory apparatus, comprising:

memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage;

each one of the strings having at least one drain-side select gate transistor on a drain-side of the one of the strings connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings; and

a control means coupled to the plurality of word lines and the plurality of bit lines and the at least one drain-side select gate transistors and configured to:

determine a respective unique select gate voltage for each of a plurality of groupings of the memory cells, the unique select gate voltage being individually adapted for each of the plurality of groupings of the memory cells such that a different unique select gate voltage is determined for each of the plurality of groupings, and

apply the respective unique select gate voltages to the at least one drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the at least one drain-side select gate transistor of the selected ones of the strings during a memory operation,

wherein determining the respective unique select gate voltages includes, for each of the plurality of groupings of memory cells, (i) setting a select gate voltage as a detection threshold voltage, (ii) selectively adjusting the detection threshold voltage and setting the select gate voltage as the adjusted detection threshold voltage, and (iii) setting the respective unique select gate voltage in response to the adjusting of the detection threshold voltage.

2. The memory apparatus as set forth in claim 1 , wherein the plurality of groupings of the memory cells include a plurality of blocks each including a plurality of the memory cells.

3. The memory apparatus as set forth in claim 1 , further including a plurality of memory die including the memory cells and wherein the plurality of groupings of the memory cells include the plurality of memory die each physically disposed separately from one another.

4. The memory apparatus as set forth in claim 1 , wherein the control means is further configured to adaptively adjust the respective unique select gate voltages based on a transistor threshold voltage of the at least one drain-side select gate transistor of each of the plurality of groupings of the memory cells.

5. The memory apparatus as set forth in claim 1 , wherein the at least one drain-side select gate transistor is configured to retain a transistor threshold voltage and the control means is further configured to:

initialize the detection threshold voltage as a predetermined detection threshold voltage in response to receiving a select gate bias searching command;

set the select gate voltage applied to the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells as the detection threshold voltage;

count a drain-side select gate quantity of the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells having the transistor threshold voltage above the detection threshold voltage;

determine whether the drain-side select gate quantity is greater than a drain-side select gate quantity detection threshold;

decrement the detection threshold voltage by a delta detection threshold voltage and return to set the select gate voltage applied to the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells as the detection threshold voltage in response to the drain-side select gate quantity not being greater than a drain-side select gate quantity detection threshold;

set the respective unique select gate voltage as an adaptive select gate voltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the drain-side select gate quantity being greater than a drain-side select gate quantity detection threshold; and

finish select gate bias searching.

6. The memory apparatus as set forth in claim 1 , wherein the control means is further configured to determine the unique select gate voltage for each of the plurality of groupings of the memory cells on a periodic basis.

7. The memory apparatus as set forth in claim 1 , wherein the control means is further configured to:

count a cycle count equal to a quantity of times the memory operation has been executed for the memory cells of one or more of the plurality of groupings of the memory cells;

determine whether the cycle count exceeds a predetermined cycle count threshold; and

determine the respective unique select gate voltages for each of the plurality of groupings of the memory cells in response to the cycle count exceeding the predetermined cycle count threshold.

8. A controller in communication with a memory apparatus including memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage, each one of the strings having at least one drain-side select gate transistor on a drain-side of the one of the strings connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings, the controller configured to:

determine a respective unique select gate voltage for each of a plurality of groupings of the memory cells, the unique select gate voltage being individually adapted for each of the plurality of groupings of the memory cells such that a different unique select gate voltage is determined for each of the plurality of groupings; and

instruct the memory apparatus to apply the respective unique select gate voltages to the at least one drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the at least one drain-side select gate transistor of the selected ones of the strings during a memory operation,

wherein determining the respective unique select gate voltages includes, for each of the plurality of groupings of memory cells, (i) setting a select gate voltage as a detection threshold voltage, (ii) selectively adjusting the detection threshold voltage and setting the select gate voltage as the adjusted detection threshold voltage, and (iii) setting the respective unique select gate voltage in response to the adjusting of the detection threshold voltage.

9. The controller as set forth in claim 8 , wherein the plurality of groupings of the memory cells include a plurality of blocks each including a plurality of the memory cells.

10. The controller as set forth in claim 8 , wherein the memory apparatus further includes a plurality of memory die including the memory cells and wherein the plurality of groupings of the memory cells include the plurality of memory die each physically disposed separately from one another.

11. The controller as set forth in claim 8 , wherein the controller is further configured to instruct the memory apparatus to adaptively adjust the respective unique select gate voltages based on a transistor threshold voltage of the at least one drain-side select gate transistor of each of the plurality of groupings of the memory cells.

12. The controller as set forth in claim 8 , wherein the at least one drain-side select gate transistor is configured to retain a transistor threshold voltage and the control means is further configured to:

initialize the detection threshold voltage as a predetermined detection threshold voltage in response to receiving a select gate bias searching command;

instruct the memory apparatus to set the select gate voltage applied to the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells as the detection threshold voltage;

instruct the memory apparatus to count a drain-side select gate quantity of the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells having the transistor threshold voltage above the detection threshold voltage;

determine whether the drain-side select gate quantity is greater than a drain-side select gate quantity detection threshold;

instruct the memory apparatus to decrement the detection threshold voltage by a delta detection threshold voltage and return to instruct the memory apparatus to set the select gate voltage applied to the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells as the detection threshold voltage in response to the drain-side select gate quantity not being greater than a drain-side select gate quantity detection threshold;

instruct the memory apparatus to set the respective unique select gate voltage as an adaptive select gate voltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the drain-side select gate quantity being greater than a drain-side select gate quantity detection threshold; and

finish select gate bias searching.

13. The controller as set forth in claim 8 , wherein the controller is further configured to determine the unique select gate voltage for each of the plurality of groupings of the memory cells on a periodic basis.

14. A method of operating a memory apparatus including memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage, each one of the strings having at least one drain-side select gate transistor on a drain-side of the one of the strings connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings, the method comprising the steps of:

determining a respective unique select gate voltage for each of a plurality of groupings of the memory cells, the unique select gate voltage being individually adapted for each of the plurality of groupings of the memory cells such that a different unique select gate voltage is determined for each of the plurality of groupings; and

applying the respective unique select gate voltages to the at least one drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the at least one drain-side select gate transistor of the selected ones of the strings during a memory operation,

wherein determining the respective unique select gate voltages includes, for each of the plurality of groupings of memory cells, (i) setting a select gate voltage as a detection threshold voltage, (ii) selectively adjusting the detection threshold voltage and setting the select gate voltage as the adjusted detection threshold voltage, and (iii) setting the respective unique select gate voltage in response to the adjusting of the detection threshold voltage.

15. The method as set forth in claim 14 , wherein the plurality of groupings of the memory cells include a plurality of blocks each including a plurality of the memory cells.

16. The method as set forth in claim 14 , wherein the memory apparatus further includes a plurality of memory die including the memory cells and wherein the plurality of groupings of the memory cells include the plurality of memory die each physically disposed separately from one another.

17. The method as set forth in claim 14 , further including the step of adaptively adjusting the respective unique select gate voltages based on a transistor threshold voltage of the at least one drain-side select gate transistor of each of the plurality of groupings of the memory cells.

18. The method as set forth in claim 14 , wherein the at least one drain-side select gate transistor is configured to retain a transistor threshold voltage, the method further including the steps of:

initializing the detection threshold voltage as a predetermined detection threshold voltage in response to receiving a select gate bias searching command;

setting the select gate voltage applied to the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells as the detection threshold voltage;

counting a drain-side select gate quantity of the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells having the transistor threshold voltage above the detection threshold voltage;

determining whether the drain-side select gate quantity is greater than a drain-side select gate quantity detection threshold;

decrementing the detection threshold voltage by a delta detection threshold voltage and returning to setting the select gate voltage applied to the at least one drain-side select gate transistor of the strings of each of the plurality of groupings of the memory cells as the detection threshold voltage in response to the drain-side select gate quantity not being greater than a drain-side select gate quantity detection threshold;

setting the respective unique select gate voltage as an adaptive select gate voltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the drain-side select gate quantity being greater than a drain-side select gate quantity detection threshold; and

finishing select gate bias searching.

19. The method as set forth in claim 14 , further including the step of determining the unique select gate voltage for each of the plurality of groupings of the memory cells on a periodic basis.

20. The method as set forth in claim 14 , further including the steps of:

counting a cycle count equal to a quantity of times the memory operation has been executed for the memory cells of one or more of the plurality of groupings of the memory cells;

determining whether the cycle count exceeds a predetermined cycle count threshold; and

determining the respective unique select gate voltages for each of the plurality of groupings of the memory cells in response to the cycle count exceeding the predetermined cycle count threshold.