SiC semiconductor substrate, method for manufacturing same, and device for manufacturing same
An object of the present invention is to provide a SiC semiconductor substrate capable of reducing a density of basal plane dislocations (BPD) in a growth layer, a manufacturing method thereof, and a manufacturing device thereof. The method includes: a strained layer removal process S 10 that removes a strained layer introduced on a surface of a SiC substrate; and an epitaxial growth process S 20 that conducts growth under a condition that a terrace width W of the SiC substrate is increased. When a SiC semiconductor substrate is manufactured in such processes, the basal plane dislocations BPD in the growth layer can be reduced, and a yield of a SiC semiconductor device can be improved.
1. A manufacturing method of SiC semiconductor substrates, the method comprising:
a strained layer removal process that removes a strained layer of a SiC substrate; and
an epitaxial growth process that conducts growth under a condition that a terrace width of the SiC substrate increases, wherein
in the epitaxial growth process, epitaxial growth is conducted under a growth condition that macro step bunching having a zigzag-shaped step end is formed when growth is conducted on a SiC substrate of which an off direction is <11−20>.
2. The manufacturing method of SiC semiconductor substrates according to claim 1 , wherein
in the epitaxial growth process, growth is conducted in a SiC—C equilibrium vapor pressure environment.
3. The manufacturing method of SiC semiconductor substrates according to claim 1 , wherein
in the epitaxial growth process, a supplying source for Si atom and a supplying source for C atom are arranged for growth such that an atomic number ratio Si/C in a supplying space for source material is 1 or less.
4. The manufacturing method of SiC semiconductor substrates according to claim 1 , wherein
in the epitaxial growth process, the SiC substrate is grown in a C-rich environment by using a CVD method.
5. The manufacturing method of SiC semiconductor substrates according to claim 1 , wherein
in the epitaxial growth process, growth is conducted on a SiC substrate on which macro step bunching is not formed.
6. The manufacturing method of SiC semiconductor substrates according to claim 1 , wherein
the epitaxial growth process is performed at a temperature of 1600° C. or higher.
7. A manufacturing method of SiC semiconductor substrates, the method comprising:
a strained layer removal process that removes a strained layer of a SiC substrate; and
an epitaxial growth process that conducts growth under a condition that a terrace width of the SiC substrate increases; and
a bunching decomposition process of decomposing the macro step bunching after the epitaxial growth process.
8. A SiC semiconductor substrate comprising:
a bulk layer having basal plane dislocations; and
a growth layer in which the basal plane dislocations are converted into other than basal plane dislocations, wherein
a conversion rate of the basal plane dislocations in the growth layer is more than 99.95%,
a surface of the bulk layer is arranged with steps having a height of one unit cell.
9. A manufacturing device of SiC semiconductor substrates, the device comprising:
a supplying space for source material for supplying Si atoms and C atoms to a SiC substrate for growth; and
a high-temperature vacuum furnace capable of heating the supplying space for source material, wherein
the supplying space for source material has a supplying source for Si atom and a supplying source for C atom, and
the supplying source for Si atom and the supplying source for C atom are arranged such that an atomic number ratio Si/C in the supplying space for source material is 1 or less,
the high-temperature vacuum furnace includes
a main heating chamber capable of heating the supplying space for source material,
a preheating chamber which is connected to the main heating chamber, and
a moving unit that moves the supplying space for source material, wherein
the moving unit is configured to be movable between the main heating chamber and the preheating chamber.
10. The manufacturing device of SiC semiconductor substrates according to claim 9 , the device further comprising:
a Si vapor pressure space in which a Si vapor pressure environment is formed, wherein
the supplying space for source material is evacuated through the Si vapor pressure space.
11. The manufacturing device of SiC semiconductor substrates according to claim 10 , the device further comprising:
a source material container which has the supplying space for source material; and
a carburizing container which has the Si vapor pressure space.
12. The manufacturing device of SiC semiconductor substrates according to claim 9 , wherein
a temperature gradient is provided in the supplying space for source material such that a temperature decreases toward the SiC substrate.
13. A method for reducing basal plane dislocations of SiC semiconductor substrates, the method comprising:
an epitaxial growth process that conducts growth under a condition that a terrace width of a SiC substrate increases, wherein
in the epitaxial growth process, epitaxial growth is conducted on the SiC substrate having a terrace width of less than 40 nm.
14. A method for reducing basal plane dislocations of SiC semiconductor substrates, the method comprising:
an epitaxial growth process that epitaxially grows a SiC substrate in a SiC—C equilibrium vapor pressure environment, wherein
in the epitaxial growth process, epitaxial growth is conducted on the SiC substrate having a terrace width of less than 40 nm.
15. The method for reducing basal plane dislocations of SiC semiconductor substrates according to claim 13 , wherein
in the epitaxial growth process, a supplying source for Si atom and a supplying source for C atom are arranged for growth such that an atomic number ratio Si/C in a supplying space for source material is 1 or less.
16. The method for reducing basal plane dislocations of SiC semiconductor substrates according to claim 13 , wherein
in the epitaxial growth process, growth is conducted on a SiC substrate on which macro step bunching is not formed.
17. A manufacturing method of SiC semiconductor substrates, the method comprising:
an epitaxial growth process that grows a SiC substrate in a SiC—C equilibrium vapor pressure environment, wherein
in the epitaxial growth process, epitaxial growth is conducted on the SiC substrate having a terrace width of less than 40 nm.
18. The manufacturing method of SiC semiconductor substrates according to claim 17 , wherein
in the epitaxial growth process, a supplying source for Si atom and a supplying source for C atom are arranged for growth such that an atomic number ratio Si/C in a supplying space for source material is 1 or less.
19. The manufacturing method of SiC semiconductor substrates according to claim 17 , wherein
in the epitaxial growth process, growth is conducted on a SiC substrate on which macro step bunching is not formed.
20. A SiC semiconductor substrate comprising:
a bulk layer which has basal plane dislocations; and
a growth layer in which the basal plane dislocations are converted into other than the basal plane dislocations, wherein
a density of the basal plane dislocations of a surface of the bulk layer is 2000 pieces/cm 2 or more, and a density of the basal plane dislocations of a surface of the growth layer is 100 pieces/cm 2 or less.
21. A SiC semiconductor substrate comprising:
a bulk layer which has basal plane dislocations; and
a growth layer in which the basal plane dislocations are converted into other than the basal plane dislocations, wherein
a density of the basal plane dislocations of a surface of the bulk layer is 2000 pieces/cm 2 or more, and a density of the basal plane dislocations of a surface of the growth layer is less than 1 piece/cm 2 .
22. A SiC semiconductor substrate comprising:
a bulk layer which has basal plane dislocations; and
a growth layer in which the basal plane dislocations are converted into other than the basal plane dislocations, wherein
a density of the basal plane dislocations of a surface of the bulk layer is 2000 pieces/cm 2 or more, and a density of the basal plane dislocations of a surface of the growth layer is 0 pieces/cm 2 .
23. A SiC semiconductor substrate which is manufactured by the manufacturing method according to claim 1 .
24. The method for reducing basal plane dislocations of SiC semiconductor substrates according to claim 14 , wherein
in the epitaxial growth process, a supplying source for Si atom and a supplying source for C atom are arranged for growth such that an atomic number ratio Si/C in a supplying space for source material is 1 or less.
25. The method for reducing basal plane dislocations of SiC semiconductor substrates according to claim 14 , wherein
in the epitaxial growth process, growth is conducted on a SiC substrate on which macro step bunching is not formed.
26. A SiC semiconductor substrate which is manufactured by the manufacturing method according to claim 17 .
27. The manufacturing method of SiC semiconductor substrates according to claim 1 , wherein
in the epitaxial growth process, growth is conducted on the SiC substrate that has been processed by the strained layer removal process and has the steps of one unit cell height on the surface.
28. The manufacturing method of SiC semiconductor substrates according to claim 17 , wherein
in the epitaxial growth process, the SiC substrate having steps of one unit cell height is grown epitaxially.
29. The method for reducing basal plane dislocations of SiC semiconductor substrates according to claim 13 , wherein
in the epitaxial growth process, the SiC substrate having steps of one unit cell height is grown epitaxially.
30. The method for reducing basal plane dislocations of SiC semiconductor substrates according to claim 14 , wherein
in the epitaxial growth process, the SiC substrate having steps of one unit cell height is grown epitaxially.