Semiconductor package and method of forming the same

1. A method of forming a semiconductor package, the method comprising:

receiving a carrier;

coating the carrier with a bonding layer;

forming a first insulator layer over the bonding layer;

forming a backside redistribution layer over the first insulator layer;

providing a pad having a hole over the backside redistribution layer;

forming a second insulator layer over the backside redistribution layer;

patterning the second insulator layer to form a recess that extends through the second insulator layer and to the pad;

filling the recess with a solder;

coupling a surface-mount device (SMD) to the solder;

providing a molding compound over the second insulator layer;

providing a via that extends to the backside redistribution layer through the molding compound and the second insulator layer; and

forming a front redistribution layer coupled to the via.

2. The method of claim 1 , further comprising providing the molding compound over the SMD.

3. The method of claim 1 , further comprising providing a chip adjacent the molding compound, wherein providing the molding compound includes

providing the molding compound over the chip, and

removing the molding compound on a top surface of the chip.

4. The method of claim 3 , further comprising forming the front redistribution layer coupled to the top surface of the chip.

5. The method of claim 1 , wherein providing the via includes:

forming a via hole that extends through the molding compound and the second insulator layer and to the backside redistribution layer; and

filling the via hole with a via material.

6. The method of claim 1 , further comprising providing a plurality of metal bumps coupled to the front redistribution layer.

7. The method of claim 1 , further comprising:

debonding the carrier from the semiconductor package; and

providing a plurality of metal bumps extending through the first insulator layer and coupled to the backside redistribution layer.

8. A method of forming a semiconductor package comprising a chip and a component, comprising:

providing a temporary bonding layer over a carrier;

forming an insulator layer over the temporary bonding;

forming a backside redistribution layer over the insulator layer;

providing a pre-solder on a pad having a hole in the backside redistribution layer;

providing the chip and the component over the backside redistribution layer;

contacting the component to the pre-solder; and

providing a molding compound over the backside redistribution layer.

9. The method of claim 8 , further comprising:

providing the molding compound over the component and adjacent to the chip;

opening a via hole in the molding compound;

providing a via in the via hole;

providing a front redistribution layer over the chip and the via to connect the chip and the component by using the backside redistribution layer, the via, and the front redistribution layer;

debonding the semiconductor package from the carrier; and

providing the semiconductor package over and connected to a printed circuit board.

10. The method of claim 8 , wherein the hole is a notch.

11. The method of claim 8 , wherein the hole is a slot.

12. The method of claim 8 , wherein the pad is a u-shape pad and the hole is an open structure.

13. The method of claim 9 , further comprising providing a plurality of metal bumps connected to the chip and the component by the front redistribution layer.

14. The method of claim 8 , wherein providing the chip and the component over the backside redistribution layer comprises providing a surface-mount device (SMD) over the backside redistribution layer.

15. The method of claim 10 , wherein the notch interrupts a laterally-extending end edge of the pad by extending longitudinally inward from the laterally-extending end edge.

16. The method of claim 15 , wherein the notch has an open end at the laterally-extending end edge of the pad and a closed end longitudinally opposite the open end.

17. The method of claim 16 , wherein the notch is located between a first side edge and a second side edge of the pad to form (i) a first tab bounded by a first side of the notch and the end edge and the first side edge and (ii) a second tab bounded by a second side of the notch and the end edge.

18. A method for forming a semiconductor package comprising a chip and a component, comprising:

providing a temporary bonding layer over a carrier;

forming an insulator layer over the temporary bonding;

forming a backside redistribution layer over the insulator layer;

providing the chip and the component over the backside redistribution layer;

providing a molding compound over the backside redistribution layer; and

providing a pre-solder on a pad having a hole in the backside redistribution layer.

19. The method of claim 1 , further comprising:

removing a portion of the second insulator layer to form a recess and to expose the backside redistribution layer;

filling the recess with a conductive material; and

providing the molding compound over the conductive material.

20. The method of claim 8 , further comprising a via interconnecting the backside and front redistribution layers.