Semiconductor device with dummy thermal features on interposer
A semiconductor device includes a bottom package, a top package stacked on the bottom package, and an interposer disposed between the bottom package and the top package. The top package is electrically connected to the interposer through a plurality of peripheral solder balls. At least a dummy thermal feature is disposed on the interposer and surrounded by the plurality of peripheral solder balls.
1. A semiconductor device, comprising:
a bottom package, wherein the bottom package comprises a semiconductor chip;
a top package stacked on the bottom package;
an interposer disposed between the bottom package and the top package, wherein the top package is electrically connected to the interposer through a plurality of peripheral solder balls; and
a plurality of dummy copper pillars arranged in an array and disposed on the interposer and surrounded by the plurality of peripheral solder balls, wherein the plurality of dummy copper pillars is formed on respective dummy pads of the interposer, wherein the dummy pads are disposed directly above the semiconductor chip and bottom surfaces of the plurality of dummy copper pillars directly contact the respective dummy pads of the interposer, and wherein each of the plurality of dummy copper pillars has a height that is smaller than that of the peripheral solder balls.
2. The semiconductor device according to claim 1 further comprises:
a capillary underfill disposed in a gap between the interposer and the top package.
3. The semiconductor device according to claim 2 , wherein the capillary underfill surrounds and protects the peripheral solder balls and is in direct contact with the plurality of dummy copper pillars.
4. The semiconductor device according to claim 1 , wherein the top package is a memory package.
5. The semiconductor device according to claim 4 , wherein the memory package comprises at least one memory chip mounted on a top substrate.
6. The semiconductor device according to claim 5 , wherein the memory chip comprises a high-bandwidth memory (HBM) or a low-power DRAM (LPDRAM) chip.
7. The semiconductor device according to claim 5 , wherein the memory chip is electrically connected to the top substrate through bond wires.
8. The semiconductor device according to claim 5 , wherein each of the plurality of the dummy metal features is not in direct contact with a bottom surface of the top substrate.
9. The semiconductor device according to claim 1 , wherein the-semiconductor chip is mounted on a bottom substrate in a flip-chip manner.
10. The semiconductor device according to claim 9 , wherein the bottom substrate comprises a three-layer or four-layer coreless embedded trace substrate.
11. The semiconductor device according to claim 9 , wherein the semiconductor chip comprises a logic die or a system on a chip (SoC) and the semiconductor chip is encapsulated by an over-mold.
12. The semiconductor device according to claim 9 , wherein the interposer comprises an interconnect structure electrically connected to through mold vias embedded in the over-mold and around the semiconductor chip.
13. The semiconductor device according to claim 1 , wherein at least some of the dummy pads are electrically connected to a ground trace or ground structure in the interposer.