IP Library › Granted Patent US 12,027,478
Granted Patent B2
US 12,027,478 · App. 17/846,596 · Granted Jul 2, 2024

Manufacturing method of semiconductor structure

Inventors: Feng-Wei Kuo (Hsinchu, TW); Wen-Shiang Liao (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L23/66H01L21/4853H01L21/4857H01L21/565H01L21/568H01L21/6835H01L23/3128H01L23/5383H01L23/5386H01L23/5389H01L24/19H01L24/20H01Q1/52H01Q9/0407H01L2221/68372H01L2223/6677H01L2224/214
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,027,478
App. No.
17/846,596
Granted
Jul 2, 2024
Kind
B2
Abstract

A method of forming a semiconductor structure includes forming a first redistribution structure including a first conductive pattern. The method further includes placing a die over the first redistribution structure. The method further includes disposing a molding material over the first redistribution structure to surround the die. The method further includes removing a portion of the molding material to form an opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a second redistribution structure over the molding material and the dielectric member, wherein the second redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.

Claims (38)

1. A method of forming a semiconductor structure, comprising:

forming a first redistribution structure including a first conductive pattern;

placing a die over the first redistribution structure;

disposing a molding material over the first redistribution structure to surround the die;

removing a portion of the molding material to form an opening, wherein removing the portion of the molding material comprises forming the opening exposing a sidewall of adjacent conductive vias of a plurality of conductive vias;

disposing a dielectric material into the opening to form a dielectric member; and

forming a second redistribution structure over the molding material and the dielectric member, wherein the second redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.

2. The method of claim 1 , wherein a dielectric constant of the dielectric material is different from a dielectric constant of the molding material.

3. The method of claim 1 , further comprising forming the plurality of conductive vias extending through the molding.

4. The method of claim 1 , further comprising:

forming a conductive bump over the second redistribution structure.

5. A method of forming a semiconductor structure, comprising:

forming a first redistribution structure including a first conductive pattern;

disposing a molding material over the first redistribution structure;

patterning the molding material to define an opening, wherein patterning the molding material comprises defining the opening exposing a sidewall of adjacent conductive vias of a plurality of conductive vias;

depositing a dielectric material into the opening to form a dielectric member; and

forming a second redistribution structure over the molding material and the dielectric member, wherein the second redistribution structure includes an antenna structure overlapping the dielectric member in a plan view.

6. The method of claim 5 , further comprising placing a die over the first redistribution structure.

7. The method of claim 6 , wherein depositing the dielectric material comprises forming the dielectric member separated from the die by a portion of the molding material.

8. The method of claim 6 , wherein forming the second redistribution structure comprises electrically connecting the antenna structure to the die.

9. The method of claim 5 , further comprising forming a plurality of conductive bumps over the second redistribution structure.

10. The method of claim 9 , wherein forming the plurality of conductive bumps comprises forming each of the plurality of conductive bumps offset from the antenna structure in a plan view.

11. The method of claim 5 , wherein disposing the molding material comprises disposing the molding material surrounding each of a plurality of conductive vias.

12. The method of claim 5 , wherein patterning the molding material comprises defining a width of the opening based on a dielectric constant of the dielectric material.

13. A method of forming a semiconductor structure, comprising:

placing a die over a first redistribution structure;

forming a plurality of conductive vias over the first redistribution structure;

disposing a molding material surrounding the die and surrounding each of the plurality of conductive vias;

removing a portion of the molding material exposing sidewalls of two adjacent conductive vias of the plurality of conductive vias to define an opening, wherein one of the two adjacent conductive vias is between the opening and the die;

disposing a dielectric material into the opening to form a dielectric member; and

forming a second redistribution structure over the molding material, wherein the second redistribution structure includes an antenna structure over the dielectric member.

14. The method of claim 13 , wherein forming the second redistribution structure comprises forming the antenna structure electrically connected to the die.

15. The method of claim 13 , further comprising forming a bump structure over the second redistribution structure.

16. The method of claim 15 , wherein forming the bump structure comprises electrically connecting the bump structure to the die.

17. The method of claim 15 , wherein forming the bump structure comprises forming the bump structure offset from the antenna structure in a plan view.

18. The method of claim 15 , wherein forming the bump structure comprises electrically connecting the bump structure to a conductive via of the plurality of conductive vias.

19. The method of claim 13 , wherein disposing the molding material comprises disposing the molding material between the die and a conductive via of the plurality of conductive vias.

20. The method of claim 13 , wherein forming the second redistribution structure comprises forming the antenna overlapping at least one conductive via of the plurality of conductive vias in a plan view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2022
From: KUO, FENG-WEI; LIAO, WEN-SHIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060276/0727 →
Continuity (3)
Division 17118017 · Dec 10, 2020
Provisional Application 63011441 · Apr 17, 2020
Related Publication 20220320022A1 · Oct 6, 2022