Static random-access memory (SRAM) bit cell with channel depopulation
Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.
1. An integrated circuit structure, comprising:
a first transistor, wherein the first transistor comprises:
a first stack of semiconductor channels, wherein a first number of active channels are in the first stack; and
a second transistor, wherein the second transistor comprises:
a second stack of semiconductor channels, wherein the second stack comprises a second number of active channels and a depopulated channel, and wherein the second number of active channels in the second stack is smaller than the first number of active channels.
2. The integrated circuit structure of claim 1 , wherein
the depopulated channel comprises a concentration of dopants that inactivates the depopulated channel.
3. The integrated circuit structure of claim 1 , wherein a total number of channels in the second stack is equal to the first number of active channels in the first stack.
4. The integrated circuit structure of claim 1 , wherein the depopulated channel comprises a dopant concentration of approximately 1e19 cm-3 or greater of a dopant of a first conductivity type that is opposite of a second conductivity type of the second transistor.
5. The integrated circuit structure of claim 1 , wherein the depopulated channel is above the plurality of active channels.
6. The integrated circuit structure of claim 1 , wherein a topmost active channel of the second transistor is aligned with a topmost active channel of the first transistor, and wherein the depopulated channel of the second transistor is adjacent to a bottommost active channel of the first transistor.
7. The integrated circuit structure of claim 1 , wherein the first transistor and the second transistor are nanoribbon or nanowire transistors.
8. A computing device, comprising:
a board;
an electronic package coupled to the board; and
a die electrically coupled to the electronic package, wherein the die comprises:
a first transistor, wherein the first transistor comprises:
a first stack of semiconductor channels, wherein a first number of active channels are in the first stack; and
a second transistor, wherein the second transistor comprises:
a second stack of semiconductor channels, wherein the second stack comprises a second number of active channels and a depopulated channel, and wherein the second number of active channels in the second stack is smaller than the first number of active channels.
9. The computing device of claim 8 , wherein the depopulated channel comprises a concentration of dopants that inactivates the depopulated channel, and wherein a total number of channels in the second stack is equal to the first number of active channels in the first stack.
10. The computing device of claim 8 , wherein a topmost active channel of the second transistor is aligned with a topmost active channel of the first transistor, and wherein the depopulated channel of the second transistor is adjacent to a bottommost active channel of the first transistor.
11. The computing device of claim 8 , further comprising:
a memory coupled to the board.
12. The computing device of claim 8 , further comprising:
a communication chip coupled to the board.
13. An integrated circuit structure, comprising:
a first transistor, wherein the first transistor comprises:
a first stack of semiconductor channels, wherein a first number of active channels are in the first stack; and
a second transistor, wherein the second transistor comprises:
a second stack of semiconductor channels, wherein a second number of active channels in the second stack is smaller than the first number of active channels, wherein a topmost active channel of the second transistor is aligned with a topmost active channel of the first transistor, and wherein a depopulated region of the second transistor is adjacent to a bottommost active channel of the first transistor.
14. A computing device, comprising:
a board;
an electronic package coupled to the board; and
a die electrically coupled to the electronic package, wherein the die comprises:
a first transistor, wherein the first transistor comprises:
a first stack of semiconductor channels, wherein a first number of active channels are in the first stack; and
a second transistor, wherein the second transistor comprises:
a second stack of semiconductor channels, wherein a second number of active channels in the second stack is smaller than the first number of active channels, wherein a topmost active channel of the second transistor is aligned with a topmost active channel of the first transistor, and wherein a depopulated region of the second transistor is adjacent to a bottommost active channel of the first transistor.