Gate driver and display device having the same
A gate driver includes stages. Each stage includes: a first output part for outputting a carry signal in response to a voltage of a first node; a first input part for controlling the voltage of the first node in response to a previous carry signal; a second input part for controlling the voltage of the first node in response to a first next carry signal; a second output part for outputting a scan signal in response to the voltage of the first node; a third output part for outputting a sensing signal in response to the voltage of the first node; and a scan signal control part for applying a first low power voltage to an output terminal of the second output part to which the scan signal is output in response to a second next carry signal of which a pulse is generated before the first next carry signal.
1. A gate driver comprising a plurality of stages, wherein each of the stages includes:
a first output part configured to output a carry signal in response to a voltage of a first node;
a first input part configured to control the voltage of the first node in response to a previous carry signal;
a second input part configured to control the voltage of the first node in response to a first next carry signal;
a second output part configured to output a scan signal in response to the voltage of the first node;
a third output part configured to output a sensing signal in response to the voltage of the first node; and
a scan signal control part configured to apply a first low power voltage to an output terminal of the second output part to which the scan signal is output in response to a second next carry signal of which a pulse is generated before a pulse of the first next carry signal,
wherein the first output part includes:
a 2-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a carry clock signal, and a second electrode connected to an output terminal of the first output part; and
a 2-2th transistor including a control electrode connected to a second node, a first electrode configured to receive a second low power voltage, and a second electrode connected to the output terminal of the first output part,
wherein the second output part includes:
a 3-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a scan clock signal, and a second electrode connected to the output terminal of the second output part; and
a 3-2th transistor including a control electrode connected to the second node, a first electrode configured to receive the first low power voltage, and a second electrode connected to the output terminal of the second output part, and
wherein the third output part includes:
a 4-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a sensing clock signal, and a second electrode connected to an output terminal of the third output part; and
a 4-2th transistor including a control electrode connected to the second node, a first electrode configured to receive the first low power voltage, and a second electrode connected to the output terminal of the third output part,
wherein the output terminal of the first output part is directly connected to only-the 2-1th transistor and the 2-2th transistor, and
wherein the output terminal of the third output part is directly connected to only the 4-1th transistor and the 4-2th transistor.
2. The gate driver of claim 1 , wherein the scan signal control part includes:
a first transistor including a control electrode configured to receive the second next carry signal, a first electrode configured to receive the first low power voltage, and a second electrode connected to the output terminal of the second output part.
3. The gate driver of claim 1 , wherein the first low power voltage is greater than the second low power voltage.
4. The gate driver of claim 1 , wherein the second output part further includes:
a first capacitor including a first electrode connected to the first node and a second electrode connected to the output terminal of the second output part, and
wherein the third output part further includes:
a second capacitor including a first electrode connected to the first node and a second electrode connected to the output terminal of the third output part.
5. The gate driver of claim 1 , wherein the first input part includes:
a 5-1th transistor including a control electrode configured to receive the previous carry signal, a first electrode configured to receive the previous carry signal, and a second electrode connected to a third node; and
a 5-2th transistor including a control electrode configured to receive the previous carry signal, a first electrode connected to the third node, and a second electrode connected to the first node, and
wherein the second input part includes:
a 6-1th transistor including a control electrode configured to receive the first next carry signal, a first electrode connected to the third node, and a second electrode connected to the first node; and
a 6-2th transistor including a control electrode configured to receive the first next carry signal, a first electrode configured to receive the second low power voltage, and a second electrode connected to the third node.
6. The gate driver of claim 5 , wherein each of the stages further includes:
a first control part configured to control a voltage of the second node in response to the voltage of the first node;
a second control part configured to control the voltage of the first node in response to the voltage of the second node; and
a third control part configured to control the voltage of the second node in response to the previous carry signal.
7. The gate driver of claim 6 , wherein each of the stages further includes:
a fourth control part configured to control the voltage of the first node in response to a start signal.
8. The gate driver of claim 7 , wherein the first control part includes:
a 7-1th transistor including a control electrode configured to receive a first scan control signal, a first electrode configured to receive the first scan control signal, and a second electrode connected to a first electrode of a 7-2th transistor;
the 7-2th transistor including a control electrode configured to receive the first scan control signal, the first electrode connected to the second electrode of the 7-1th transistor, and a second electrode connected to a fourth node;
an eighth transistor including a control electrode connected to the fourth node, a first electrode configured to receive the first scan control signal, and a second electrode connected to the second node;
a ninth transistor including a control electrode connected to the first node, a first electrode configured to receive a third low power voltage, and a second electrode connected to the fourth node; and
a tenth transistor including a control electrode connected to the first node, a first electrode configured to receive the second low power voltage, and a second electrode connected to the second node.
9. The gate driver of claim 8 , wherein the third low power voltage is the same as the first low power voltage.
10. The gate driver of claim 8 , wherein the first scan control signal is a gate-on voltage.
11. The gate driver of claim 8 , wherein the second control part includes:
an 11-1th transistor including a control electrode connected to the second node, a first electrode connected to the third node, and a second electrode connected to the first node; and
an 11-2th transistor including a control electrode connected to the second node, a first electrode configured to receive the second low power voltage, and a second electrode connected to the third node,
wherein the third control part includes:
a twelfth transistor including a control electrode configured to receive the previous carry signal, a first electrode configured to receive the second low power voltage, and a second electrode connected to the second node, and
wherein the fourth control part includes:
a 13-1th transistor including a control electrode configured to receive the start signal, a first electrode connected to the third node, and a second electrode connected to the first node; and
a 13-2th transistor including a control electrode configured to receive the start signal, a first electrode configured to receive the second low power voltage, and a second electrode connected to the third node.
12. The gate driver of claim 11 , wherein each of the stages further includes:
a leakage control part configured to apply a second scan control signal to the third node in response to the voltage of the first node.
13. The gate driver of claim 12 , wherein the second scan control signal is a gate-on voltage.
14. The gate driver of claim 12 , wherein the leakage control part includes:
a 14-1th transistor including a control electrode connected to the first node, a first electrode configured to receive the second scan control signal, and a second electrode connected to a first electrode of a 14-2th transistor; and
the 14-2th transistor including a control electrode connected to the first node, the first electrode connected to the second electrode of the 14-1th transistor, and a second electrode connected to the third node.
15. The gate driver of claim 1 , wherein at least one of the stages is selected, and
wherein each of the stages includes a sensing circuit configured to apply a gate-on voltage to the first node of the selected stage in a blank period.
16. The gate driver of claim 1 , wherein an on-duty ratio of the scan signal is smaller than an on-duty ratio of the sensing signal.
17. A display device comprising:
a display panel including pixels connected to data lines;
a gate driver including a plurality of stages;
a data driver configured to apply data voltages to the pixels; and
a timing controller configured to control the gate driver and the data driver,
wherein each of the stages includes:
a first output part configured to output a carry signal in response to a voltage of a first node;
a first input part configured to control the voltage of the first node in response to a previous carry signal;
a second input part configured to control the voltage of the first node in response to a first next carry signal;
a second output part configured to output a scan signal in response to the voltage of the first node;
a third output part configured to output a sensing signal in response to the voltage of the first node; and
a scan signal control part configured to apply a first low power voltage to an output terminal of the second output part to which the scan signal is output in response to a second next carry signal of which a pulse is generated before a pulse of the first next carry signal,
wherein the first output part includes:
a 2-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a carry clock signal, and a second electrode connected to an output terminal of the first output part; and
a 2-2th transistor including a control electrode connected to a second node, a first electrode configured to receive a second low power voltage, and a second electrode connected to the output terminal of the first output part,
wherein the second output part includes:
a 3-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a scan clock signal, and a second electrode connected to the output terminal of the second output part; and
a 3-2th transistor including a control electrode connected to the second node, a first electrode configured to receive the first low power voltage, and a second electrode connected to the output terminal of the second output part, and
wherein the third output part includes:
a 4-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a sensing clock signal, and a second electrode connected to an output terminal of the third output part; and
a 4-2th transistor including a control electrode connected to the second node, a first electrode configured to receive the first low power voltage, and a second electrode connected to the output terminal of the third output part,
wherein the output terminal of the first output part is directly connected to only the 2-1th transistor and the 2-2th transistor, and
wherein the output terminal of the third output part is directly connected to only the 4-1th transistor and the 4-2th transistor.
18. The display device of claim 17 , wherein each of the pixels includes:
a driving transistor including a control electrode connected to a fifth node, a first electrode configured to receive a first power voltage, and a second electrode connected to a sixth node;
a write transistor including a control electrode configured to receive the scan signal, a first electrode configured to receive a corresponding data voltage of the data voltages, and a second electrode connected to the fifth node;
a sensing transistor including a control electrode configured to receive the sensing signal, a first electrode connected to a sensing line, and a second electrode connected to the sixth node;
a storage capacitor including a first electrode connected to the fifth node and a second electrode connected to the sixth node; and
a light emitting element including a first electrode connected to the sixth node and a second electrode configured to receive a second power voltage.