Scan driver, display device using the same, and electronic device including the same
A scan driver includes a plurality of stage circuits. A last stage circuit among the plurality of stage circuits includes a self-initialization signal unit charging a node of the last stage circuit to a first level in response to a clock signal an initialization initializing the last stage circuit when the node is at the first level.
1 . A scan driver comprising:
a plurality of stage circuits,
wherein a last stage circuit among the plurality of stage circuits comprises:
a self-initialization signal circuit charging a first node of the last stage circuit to a first level in response to a first clock signal;
an initialization circuit initializing the last stage circuit when the first node is at the first level;
an input circuit charging a second node of the last stage circuit to the first level in response to a gate voltage of a first logic level input to a first input terminal;
an inverter circuit changing a voltage level of a third node of the last stage circuit according to a voltage level of the second node;
an initialization control circuit controlling an operation of the initialization circuit in response to the voltage level of the third node; and
an output circuit outputting a carry signal when the second node is at the first level,
wherein the carry signal initializes a previous stage circuit.
2 . The scan driver of claim 1 , wherein the initialization circuit comprises:
a first transistor having a first electrode connected to the second node, a gate electrode connected to the first node, and a second electrode connected to the third node; and
a second transistor having a first electrode connected to the third node, a gate electrode connected to the first node, and a second electrode connected to a first input terminal receiving a first reset power voltage.
3 . The scan driver of claim 2 , wherein the self-initialization signal circuit comprises:
a third transistor having a first electrode connected to a second input terminal receiving the first clock signal, a gate electrode connected to the second node, and a second electrode connected to the first node;
a fourth transistor having a first electrode connected to the first node, a gate electrode connected to a third input terminal receiving a carry signal from the previous stage circuit, and a second electrode connected to the first input terminal; and
a fifth transistor having a first electrode connected to the first node, and a gate electrode and a second electrode connected to the first input terminal.
4 . The scan driver of claim 2 , wherein the self-initialization signal circuit comprises:
a third transistor having a first electrode connected to a second input terminal receiving the first clock signal, a gate electrode connected to the second node, and a second electrode connected to the first node;
a fourth transistor having a first electrode connected to the first node, a gate electrode connected to a third input terminal receiving a carry signal from the previous stage circuit, and a second electrode connected to the first input terminal; and
a fifth transistor having a first electrode connected to the first node, a gate electrode connected to the inverter circuit, and a second electrode connected to the first input terminal.
5 . The scan driver of claim 4 , wherein the inverter circuit comprises a sixth transistor having a first electrode connected to the gate electrode of the fifth transistor, a gate electrode connected to the second node, and a second electrode connected to a fourth input terminal receiving a second reset power voltage.
6 . The scan driver of claim 2 , wherein the self-initialization signal circuit comprises:
a third transistor having a first electrode connected to a second input terminal receiving the first clock signal, a gate electrode connected to the second node, and a second electrode connected to the first node; and
a fourth transistor having a first electrode connected to the first node, a gate electrode connected to the inverter circuit, and a second electrode connected to the first input terminal.
7 . The scan driver of claim 6 , wherein the inverter circuit comprises a fifth transistor having a first electrode connected to the gate electrode of the fourth transistor, a gate electrode connected to the second node, and a second electrode connected to a fourth input terminal receiving a second reset power voltage.
8 . The scan driver of claim 2 , wherein the self-initialization signal circuit comprises:
a third transistor having a first electrode connected to a second input terminal receiving the first clock signal, a gate electrode connected to the second node, and a second electrode connected to the first node; and
a fourth transistor having a first electrode connected to the first node, a gate electrode connected to a third input terminal receiving a carry signal from the previous stage circuit, and a second electrode connected to the first input terminal.
9 . A display device comprising:
a display panel comprising a plurality of pixels; and
a scan driver supplying scan signals to the plurality of pixels,
wherein the scan driver comprises a plurality of stage circuits, and
wherein a last stage circuit among the plurality of stage circuits comprises:
a self-initialization signal circuit charging a first node of the last stage circuit to a first level in response to a first clock signal;
an initialization circuit initializing the last stage circuit when the first node is at the first level;
an input circuit charging a second node of the last stage circuit to the first level in response to a gate voltage of a first logic level input to a first input terminal;
an inverter circuit changing a voltage level of a third node of the last stage circuit according to a voltage level of the second node;
an initialization control circuit controlling an operation of the initialization circuit in response to the voltage level of the third node; and
an output circuit outputting a carry signal when the second node is at the first level,
wherein the carry signal initializes a previous stage circuit.
10 . The display device of claim 9 , wherein the initialization circuit comprises:
a first transistor having a first electrode connected to the second node, a gate electrode connected to the first node, and a second electrode connected to the third node; and
a second transistor having a first electrode connected to the third node, a gate electrode connected to the first node, and a second electrode connected to a first input terminal receiving a first reset power voltage.
11 . The display device of claim 10 , wherein the self-initialization signal circuit comprises:
a third transistor having a first electrode connected to a second input terminal receiving the first clock signal, a gate electrode connected to the second node, and a second electrode connected to the first node;
a fourth transistor having a first electrode connected to the first node, a gate electrode connected to a third input terminal receiving a carry signal from the previous stage circuit, and a second electrode connected to the first input terminal; and
a fifth transistor having a first electrode connected to the first node, and a gate electrode and a second electrode connected to the first input terminal.
12 . The display device of claim 10 , wherein the self-initialization signal circuit comprises:
a third transistor having a first electrode connected to a second input terminal receiving the first clock signal, a gate electrode connected to the second node, and a second electrode connected to the first node;
a fourth transistor having a first electrode connected to the first node, a gate electrode connected to a third input terminal receiving a carry signal from the previous stage circuit, and a second electrode connected to the first input terminal; and
a fifth transistor having a first electrode connected to the first node, a gate electrode connected to the inverter circuit, and a second electrode connected to the first input terminal.
13 . The display device of claim 12 , wherein the inverter circuit comprises a sixth transistor having a first electrode connected to the gate electrode of the fifth transistor, a gate electrode connected to the second node, and a second electrode connected to a fourth input terminal receiving a second reset power voltage.
14 . The display device of claim 10 , wherein the self-initialization signal circuit comprises:
a third transistor having a first electrode connected to a second input terminal receiving the first clock signal, a gate electrode connected to the second node, and a second electrode connected to the first node; and
a fourth transistor having a first electrode connected to the first node, a gate electrode connected to the inverter circuit, and a second electrode connected to the first input terminal.
15 . The display device of claim 14 , wherein the inverter circuit comprises a fifth transistor having a first electrode connected to the gate electrode of the fourth transistor, a gate electrode connected to the second node, and a second electrode connected to a fourth input terminal receiving a second reset power voltage.
16 . The display device of claim 10 , wherein the self-initialization signal circuit comprises:
a third transistor having a first electrode connected to a second input terminal receiving the first clock signal, a gate electrode connected to the second node, and a second electrode connected to the first node; and
a fourth transistor having a first electrode connected to the first node, a gate electrode connected to a third input terminal receiving a carry signal from the previous stage circuit, and a second electrode connected to the first input terminal.
17 . An electronic device comprising:
a display device for displaying an image,
wherein the display device comprises:
a display panel comprising a plurality of pixels; and
a scan driver providing a scan signal to each of the plurality of pixels,
wherein the scan driver comprises a plurality of stage circuits,
wherein a last stage circuit among the plurality of stage circuits comprises:
a self-initialization signal unit charging a first node of the last stage circuit to a first level in response to a first clock signal; and
an initialization circuit initializing the last stage circuit when the first node is at the first level;
an input circuit charging a second node of the last stage circuit to the first level in response to a gate voltage of a first logic level input to a first input terminal;
an inverter circuit changing a voltage level of a third node of the last stage circuit according to a voltage level of the second node;
an initialization control circuit controlling an operation of the initialization circuit in response to the voltage level of the third node; and
an output circuit outputting a carry signal when the second node is at the first level,
wherein the carry signal initializes a previous stage circuit.