Method for programming memory device to reduce retention error
A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.
1. A memory device, comprising:
memory cells; and
a control circuit coupled to the memory cells and configured to:
perform program operations to program the memory cells with at least one first program voltage;
determine whether threshold voltages of the memory cells are greater than a verification voltage after programming the memory cells after each of the program operations; and
in response to a threshold voltage of a first memory cell of the memory cells is greater than a verification voltage that corresponds to a first programming state not lower than a predetermined programming state, reprogram the first memory cell with the at least one first program voltage,
wherein the first memory cell has been programmed to the first programming state before reprogramming the first memory cell.
2. The memory device of claim 1 , wherein the control circuit is configured to:
reprogram the first memory cell only once.
3. The memory device of claim 1 , wherein the threshold voltage of the first memory cell is not greater than the verification voltage before programming the memory cells.
4. The memory device of claim 1 , wherein the control circuit is configured to:
in response to the threshold voltage of the first memory cell of the memory cells is determined to newly become greater than the verification voltage that corresponds to the first programming state not lower than the predetermined programming state, reprogram the first memory cell.
5. The memory device of claim 1 , wherein the control circuit is further configured to:
program at least a third memory cell of the memory cells, wherein the threshold voltage of the third memory cell is not greater than the verification voltage after programming the memory cells.
6. The memory device of claim 1 , wherein the verification voltage is smaller than a predetermined verification voltage, wherein the predetermined verification voltage corresponds to the predetermined programming state.
7. A memory device, comprising:
memory cells; and
a control circuit coupled to the memory cells and configured to:
perform program operations to program the memory cells with at least one first program voltage;
determine whether threshold voltages of the memory cells are greater than a verification voltage after programming the memory cells after each of the program operations; and
in response to determining that a predetermined number of program operations have been performed and that a threshold voltage of a first memory cell of the memory cells is greater than a verification voltage that corresponds to a first programming state not lower than a predetermined programming state, reprogram the first memory cell with the at least one first program voltage,
wherein the first memory cell has been programmed to the first programming state before reprogramming the first memory cell.
8. The memory device of claim 7 , wherein the control circuit is configured to:
reprogram the first memory cell only once.
9. The memory device of claim 7 , wherein the threshold voltage of the first memory cell is not greater than the verification voltage before programming the memory cells.
10. The memory device of claim 7 , wherein the control circuit is further configured to:
program at least a third memory cell of the memory cells, wherein the threshold voltage of the third memory cell is not greater than the verification voltage after programming the memory cells.
11. A memory device, comprising:
memory cells; and
a control circuit coupled to the memory cells and configured to:
perform program operations to program the memory cells with at least one first program voltage;
determine whether threshold voltages of the memory cells are greater than a first verification voltage after programming the memory cells after each of the program operations;
in response to determining that a threshold voltage of at least a first memory cell of the memory cells is greater than the first verification voltage, increase the first verification voltage to a second verification voltage, wherein the first verification voltage corresponds to a first programming state not lower than a predetermined programming state; and
reprogram the first memory cell with the at least one first program voltage.
12. The memory device of claim 11 , wherein the control circuit is further configured to:
in response to the threshold voltage of the first memory cell of the memory cells is determined to newly become greater than the first verification voltage that corresponds to the first programming state not lower than the predetermined programming state, reprogram the first memory cell.
13. A memory device, comprising:
memory cells; and
a control circuit coupled to the memory cells and configured to:
perform program operations to program the memory cells with at least one first program voltage;
determine whether threshold voltages of the memory cells are greater than a first verification voltage after programming the memory cells after each of the program operations;
in response to determining that a predetermined number of program operations have been performed and that a threshold voltage of a first memory cell of the memory cells is greater than the first verification voltage that corresponds to a first programming state not lower than a predetermined programming state, increase a first verification voltage to a second verification voltage; and
reprogram the first memory cell with the at least one first program voltage.
14. The memory device of claim 13 , wherein the control circuit is further configured to:
in response to the threshold voltage of the first memory cell of the memory cells is determined to newly become greater than the verification voltage that corresponds to the first programming state not lower than the predetermined programming state, reprogram the first memory cell.
15. A method of operating a memory device, comprising:
performing program operations to program memory cells with at least one first program voltage;
determining whether threshold voltages of the memory cells are greater than a verification voltage after programming the memory cells after each of the program operations; and
in response to a threshold voltage of a first memory cell of the memory cells is greater than a verification voltage that corresponds to a first programming state not lower than a predetermined programming state, reprogramming the first memory cell with the at least one first program voltage,
wherein the first memory cell has been programmed to the first programming state before reprogramming the first memory cell.
16. The method of claim 15 , wherein reprogramming the first memory cell of the memory cells only once.
17. The method of claim 15 , wherein the threshold voltage of the first memory cell is not greater than the verification voltage before programming the memory cells.
18. The method of claim 15 , further comprising:
in response to the threshold voltage of the first memory cell of the memory cells is determined to newly become greater than the verification voltage that corresponds to the first programming state not lower than the predetermined programming state, reprogramming the first memory cell.
19. The method of claim 15 , further comprising:
programming at least a third memory cell of the memory cells, wherein the threshold voltage of the third memory cell is not greater than the verification voltage after programming the memory cells.