Package-on-package (PoP) semiconductor package and electronic system including the same
A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area.
1. A package-on-package (PoP) semiconductor package, comprising:
an upper package; and
a lower package, the lower package including:
a first semiconductor device in a first area;
a second semiconductor device in a second area; and
a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, a memory management vertical interconnection, a power vertical interconnection, and a ground vertical interconnection,
wherein the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection are adjacent to the first semiconductor device at a same vertical level,
wherein the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection are laterally spaced apart from the first semiconductor device, and
wherein the power vertical interconnection and the ground vertical interconnection are not between the first semiconductor device and the second semiconductor device.
2. The PoP semiconductor package as claimed in claim 1 , wherein at least one of the data input-output vertical interconnection and the memory management vertical interconnection is between the first semiconductor device and the second semiconductor device.
3. The PoP semiconductor package as claimed in claim 1 , wherein at least one of the CA vertical interconnection and the data input-output vertical interconnection is between the first semiconductor device and the second semiconductor device.
4. The PoP semiconductor package as claimed in claim 1 , wherein:
the first semiconductor device includes a first side surface and a second side surface parallel to the first side surface, the second side surface facing the second semiconductor device, and
at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection is adjacent to the first side surface.
5. The PoP semiconductor package as claimed in claim 4 , wherein:
the second semiconductor device includes a first side facing the first semiconductor device and a second side opposite to the first side, and
at least one of the power vertical interconnection and the ground vertical interconnection is among side surfaces of the second semiconductor device on a portion facing the second side.
6. The PoP semiconductor package as claimed in claim 1 , further comprising a dummy vertical interconnection, the dummy vertical interconnection not being between the first semiconductor device and the second semiconductor device.
7. The PoP semiconductor package as claimed in claim 1 , wherein the first semiconductor device is an application processor (AP) chip and the second semiconductor device is a power management integrated circuit chip.
8. The PoP semiconductor package as claimed in claim 1 , wherein the upper package includes a non-volatile memory device and a memory controller, the memory controller being configured to control the non-volatile memory device in accordance with a control of the first semiconductor device of the lower package.
9. The PoP semiconductor package as claimed in claim 1 , wherein the upper package includes a volatile memory device and a memory controller, the memory controller being configured to control the volatile memory device in accordance with a control of the first semiconductor device of the lower package.
10. The PoP semiconductor package as claimed in claim 1 , wherein the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection have a regular arrangement of equilateral triangles.
11. The PoP semiconductor package as claimed in claim 1 , wherein the first semiconductor device and the second semiconductor device are on a lower package substrate and are encapsulated by an encapsulation material.
12. The PoP semiconductor package as claimed in claim 11 , wherein an upper surface of the encapsulation material is spaced apart from and opposed to a lower surface of the upper package.
13. The PoP semiconductor package as claimed in claim 1 , wherein:
the second semiconductor device includes a first side facing the first semiconductor device and a second side opposite to the first side, and
the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection are not, among side surfaces of the second semiconductor device, on a portion facing the second side.
14. The PoP semiconductor package as claimed in claim 13 , wherein the CA vertical interconnection is between the first semiconductor device and the second semiconductor device.
15. The PoP semiconductor package as claimed in claim 14 , wherein:
the first semiconductor device includes a first side surface and a second side surface parallel to the first side surface, the second side surface facing the second semiconductor device,
the data input-output vertical interconnection is adjacent to the first side surface, and
the memory management vertical interconnection is adjacent to a third side surface of the first semiconductor device, the third side surface being between the first side surface and the second side surface.
16. A package-on-package (PoP) semiconductor package, comprising:
an upper package; and
a lower package, the lower package including:
a first semiconductor device in a first area;
a second semiconductor device in a second area; and
a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, a memory management vertical interconnection, a power vertical interconnection, and a ground vertical interconnection,
wherein the lower package includes an upper redistribution layer and a lower redistribution layer which are respectively adjacent to an upper surface and a lower surface of the lower package,
wherein the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection are adjacent to the first semiconductor device, and
wherein the power vertical interconnection and the ground vertical interconnection are not between the first semiconductor device and the second semiconductor device.
17. The PoP semiconductor package as claimed in claim 16 , wherein the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection are not, among the side surfaces of the second semiconductor device, on a portion facing a side opposite to a side facing the first semiconductor device.
18. The PoP semiconductor package as claimed in claim 17 , wherein the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection have a regular arrangement of equilateral triangles.
19. A package-on-package (PoP) semiconductor package, comprising:
an upper package; and
a lower package, the lower package including:
a first semiconductor device in a first area;
a second semiconductor device in a second area; and
a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, a memory management vertical interconnection, a power vertical interconnection, and a ground vertical interconnection, wherein:
the lower package includes an upper redistribution layer and a lower redistribution layer which are respectively adjacent to an upper surface and a lower surface of the lower package,
the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection are adjacent to the first semiconductor device,
the CA vertical interconnection is between the first semiconductor device and the second semiconductor device,
the power vertical interconnection and the ground vertical interconnection are not between the first semiconductor device and the second semiconductor device, and
the first semiconductor device includes a first side surface and a second side surface parallel to the first side surface, the second side surface facing the second semiconductor device, and the data input-output vertical interconnection is adjacent to the first side surface.
20. The PoP semiconductor package as claimed in claim 19 , wherein:
the upper package includes a non-volatile memory device and a memory controller, the memory controller being configured to control the non-volatile memory device in accordance with a control of the first semiconductor device of the lower package, and
the first semiconductor device is an application processor (AP) chip and the second semiconductor device is a power management integrated circuit chip.