IP Library Granted Patent US 12,034,064
Granted Patent B2
US 12,034,064 · App. 17/111,838 · Granted Jul 9, 2024

Semiconductor device and method for manufacturing the same

Inventors: Shunpei Yamazaki (Setagaya, JP); Hidekazu Miyairi (Isehara, JP); Kengo Akimoto (Atsugi, JP); Kojiro Shiraishi (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/66969H01L21/46H01L27/1225H01L29/7869
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Quick Facts
Patent No.
US 12,034,064
App. No.
17/111,838
Granted
Jul 9, 2024
Kind
B2
Abstract

It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

Claims (38)

1. A semiconductor device comprising:

a thin film transistor comprising:

a metal gate electrode over a glass substrate;

a gate insulating layer over the metal gate electrode;

an oxide semiconductor layer over the gate insulating layer;

a first metal layer over the oxide semiconductor layer;

a second metal layer over and in contact with the first metal layer;

a third metal layer over the oxide semiconductor layer; and

a fourth metal layer over and in contact with the third metal layer;

an insulating layer over the oxide semiconductor layer, the second metal layer, and the fourth metal layer, the insulating layer being in contact with a top surface of the oxide semiconductor layer; and

a pixel electrode over the insulating layer,

wherein a first gap between the first metal layer and the third metal layer is smaller than a second gap between the second metal layer and the fourth metal layer,

wherein the first gap is a distance between an upper end portion of the first metal layer and an upper end portion of the third metal layer, and the second gap is a distance between a lower end portion of the second metal layer and a lower end portion of the fourth metal layer,

wherein each of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer overlaps with the oxide semiconductor layer,

wherein each of the first metal layer and the second metal layer extends beyond an edge of the oxide semiconductor layer, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

2. The semiconductor device according to claim 1 , wherein the first metal layer is in contact with a top surface of the gate insulating layer.

3. A semiconductor device comprising:

a thin film transistor comprising:

a metal gate electrode over a glass substrate;

a gate insulating layer over the metal gate electrode;

an oxide semiconductor layer over the gate insulating layer;

a first metal layer over the oxide semiconductor layer;

a second metal layer over and in contact with the first metal layer;

a third metal layer over the oxide semiconductor layer; and

a fourth metal layer over and in contact with the third metal layer;

an insulating layer over the oxide semiconductor layer, the second metal layer, and the fourth metal layer, the insulating layer being in contact with a top surface of the oxide semiconductor layer; and

a pixel electrode over the insulating layer,

wherein a first gap between the first metal layer and the third metal layer is smaller than a second gap between the second metal layer and the fourth metal layer,

wherein the first gap is a distance between an upper end portion of the first metal layer and an upper end portion of the third metal layer, and the second gap is a distance between a lower end portion of the second metal layer and a lower end portion of the fourth metal layer,

wherein each of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer overlaps with the oxide semiconductor layer,

wherein each of the first metal layer and the second metal layer extends beyond an edge of the oxide semiconductor layer,

wherein the pixel electrode is electrically connected to the second metal layer through an opening of the insulating layer,

wherein the opening of the insulating layer comprises a region not overlapping with the oxide semiconductor layer, and

wherein the second metal layer comprises copper.

4. The semiconductor device according to claim 3 , wherein the first metal layer is in contact with a top surface of the gate insulating layer.

5. The semiconductor device according to claim 3 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

6. The semiconductor device according to claim 5 , wherein the first metal layer is in contact with a top surface of the gate insulating layer.

Priority Claims (1)
JP 2008-197145 · Jul 31, 2008 · national
Continuity (6)
Continuation 15656173 · Jul 21, 2017
Continuation 14820008 · Aug 6, 2015
Division 13346963 · Jan 10, 2012
Division 13013054 · Jan 25, 2011
Continuation 12511285 · Jul 29, 2009
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