IP Library Granted Patent US 12,046,604
Granted Patent B2
US 12,046,604 · App. 17/204,460 · Granted Jul 23, 2024

Liquid crystal display device, EL display device, and manufacturing method thereof

Inventors: Shunpei Yamazaki (Tokyo, JP); Jun Koyama (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1259G02F1/133345G02F1/136227G02F1/136286G02F1/1368H01L27/1225H01L27/124H01L27/1255H01L27/127H01L27/1288G02F1/13629G02F1/136295G02F2201/123H01L27/1222
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Quick Facts
Patent No.
US 12,046,604
App. No.
17/204,460
Granted
Jul 23, 2024
Kind
B2
Abstract

A display device is manufactured with five photolithography steps: a step of forming a gate electrode, a step of forming a protective layer for reducing damage due to an etching step or the like, a step of forming a source electrode and a drain electrode, a step of forming a contact hole, and a step of forming a pixel electrode. The display device includes a groove portion which is formed in the step of forming the contact hole and separates the semiconductor layer.

Claims (57)

1. A semiconductor device comprising:

a semiconductor layer;

an insulating layer over the semiconductor layer;

a first wiring over the insulating layer, the first wiring electrically connected to the semiconductor layer; and

a conductive layer over the insulating layer,

wherein the semiconductor layer includes a first region configured to be a channel formation region of a first transistor, a second region configured to be a channel formation region of a second transistor, and a third region between the first region and the second region,

wherein the channel formation region of the first transistor is electrically connected to a gate electrode of the second transistor via the conductive layer,

wherein the second transistor is electrically connected to a first light-emitting element,

wherein the first transistor, the second transistor, and the first light-emitting element are provided in a first pixel,

wherein the second transistor is adjacent to the first transistor, and

wherein the conductive layer is in contact with a side surface of the semiconductor layer via an opening of the semiconductor layer.

2. The semiconductor device according to claim 1 , wherein at least the third region of the semiconductor layer is not overlapped with the first wiring.

3. The semiconductor device according to claim 1 , further comprising:

a second wiring electrically connected to the channel formation region of the second transistor via an opening of the insulating layer.

4. The semiconductor device according to claim 3 , further comprising:

a capacitor comprising a part of the gate electrode of the second transistor and a part of the second wiring.

5. The semiconductor device according to claim 1 , wherein the semiconductor layer comprises polycrystalline silicon.

6. The semiconductor device according to claim 1 , wherein the first wiring has a stacked structure using metal materials selected from molybdenum, titanium, tungsten, tantalum, aluminum, copper, chromium, neodymium, and scandium.

7. A semiconductor device comprising:

a first insulating layer;

a semiconductor layer over the first insulating layer;

a second insulating layer over the semiconductor layer;

a first wiring over the second insulating layer, the first wiring electrically connected to the semiconductor layer; and

a conductive layer over the second insulating layer,

wherein the semiconductor layer includes a first region configured to be a channel formation region of a first transistor, a second region configured to be a channel formation region of a second transistor, and a third region between the first region and the second region,

wherein the channel formation region of the first transistor is electrically connected to a gate electrode of the second transistor via the conductive layer,

wherein the second transistor is electrically connected to a first light-emitting element,

wherein the first transistor, the second transistor, and the first light-emitting element are provided in a first pixel,

wherein the second transistor is adjacent to the first transistor,

wherein the conductive layer is in contact with the first insulating layer via an opening of the second insulating layer and an opening of the semiconductor layer, and

wherein the conductive layer is in contact with a side surface of the semiconductor layer in the opening of the semiconductor layer.

8. The semiconductor device according to claim 7 , wherein at least the third region of the semiconductor layer is not overlapped with the first wiring.

9. The semiconductor device according to claim 7 , further comprising:

a second wiring electrically connected to the channel formation region of the second transistor via an opening of the second insulating layer.

10. The semiconductor device according to claim 9 , further comprising:

a capacitor comprising a part of the gate electrode of the second transistor and a part of the second wiring.

11. The semiconductor device according to claim 7 , wherein the semiconductor layer comprises polycrystalline silicon.

12. The semiconductor device according to claim 7 , wherein the first wiring has a stacked structure using metal materials selected from molybdenum, titanium, tungsten, tantalum, aluminum, copper, chromium, neodymium, and scandium.

13. A semiconductor device comprising:

a semiconductor layer;

an insulating layer over the semiconductor layer;

a first wiring over the insulating layer, the first wiring electrically connected to the semiconductor layer; and

a conductive layer over the insulating layer,

wherein the semiconductor layer includes a channel formation region of a first transistor, a channel formation region of a second transistor, a channel formation region of a third transistor, and a channel formation region of a fourth transistor,

wherein the channel formation region of the first transistor is electrically connected to a gate electrode of the second transistor via the conductive layer,

wherein the second transistor is electrically connected to a first light-emitting element,

wherein the first transistor, the second transistor, and the first light-emitting element are provided in a first pixel,

wherein the channel formation region of the third transistor is electrically connected to a gate electrode of the fourth transistor,

wherein the fourth transistor is electrically connected to a second light-emitting element,

wherein the third transistor, the fourth transistor, and the second light-emitting element are provided in a second pixel adjacent to the first pixel, and

wherein the conductive layer is in contact with a side surface of the semiconductor layer in an opening of the semiconductor layer.

14. The semiconductor device according to claim 13 , wherein the first pixel and the second pixel are electrically connected to the first wiring.

15. The semiconductor device according to claim 13 , further comprising:

a second wiring electrically connected to the channel formation region of the second transistor via an opening of the insulating layer; and

a capacitor comprising a part of the gate electrode of the second transistor and a part of the second wiring.

16. The semiconductor device according to claim 13 , wherein the semiconductor layer comprises polycrystalline silicon.

17. The semiconductor device according to claim 13 , wherein the first wiring has a stacked structure using metal materials selected from molybdenum, titanium, tungsten, tantalum, aluminum, copper, chromium, neodymium, and scandium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2021
From: YAMAZAKI, SHUNPEI; KOYAMA, JUN
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 055627/0546 →
Priority Claims (2)
JP 2011-247360 · Nov 11, 2011 · national
JP 2011-247367 · Nov 11, 2011 · national
Continuity (3)
Continuation 15435693 · Feb 17, 2017
Continuation 13667271 · Nov 2, 2012
Related Publication 20210202542A1 · Jul 1, 2021
Cited By (1)
US 12,432,979