Semiconductor package and method

1. A semiconductor structure, comprising:

a first redistribution structure, the first redistribution structure comprising a first redistribution layer, the first redistribution layer comprising a first dielectric layer and a first metallization layer;

a second redistribution structure, the second redistribution structure including:

a first local interconnect component disposed on the first redistribution structure, the first local interconnect component including: a bottommost dielectric layer having embedded therein a first conductive via with a vertically extending longitudinal axis; at least one intermediate dielectric layer atop the bottom dielectric layer and having embedded therein a conductive line with a first horizontally-extending longitudinal axis and further having embedded therein a second conductive via with a vertically-extending longitudinal axis; a topmost dielectric layer having embedded therein a second conductive line with a horizontally-extending longitudinal axis and further having embedded therein a third conductive via with a vertically-extending longitudinal axis; and a first conductive connector with a vertically-extending longitudinal axis and being in physical contact with the third conductive via and extending above a topmost surface of the topmost dielectric layer; the first conductive via with a vertically-extending longitudinal axis having a bottommost surface that is planar with a bottommost surface of the bottommost dielectric layer; the third conductive via with a vertically-extending longitudinal axis having a topmost surface that is planar with a topmost surface of the topmost dielectric layer, sidewalls of the first local interconnect component being surrounded by an encapsulant,

a conductive through via extending from the top to the bottom of the encapsulant, wherein a topmost surface of the conductive through via is planar with a topmost surface of the encapsulant and is planar with a bottommost surface of the first conductive connector, and further wherein the conductive through via has a constant cross-section width from its topmost surface to its bottommost surface; and

a first interconnect structure over the topmost surface of the first local interconnect component, the first interconnect structure comprising a first bond pad and a second bond pad, the first bond pad being electrically coupled to the second bond pad through the first local interconnect component.

2. The semiconductor structure of claim 1 further comprising:

a first integrated circuit die physically and electrically coupled to the first interconnect structure opposite the first local interconnect component, the first integrated circuit die being electrically coupled to the first bond pad of the first interconnect structure; and

a second integrated circuit die physically and electrically coupled to the first interconnect structure opposite the first local interconnect component, the second integrated circuit die being adjacent to the first integrated circuit die, the second integrated circuit die being electrically coupled to the second bond pad of the first interconnect structure.

3. The semiconductor structure of claim 1 wherein the conductive through via is bonded to a conductive feature of the first redistribution structure, a top surface of the conductive through via being bonded to a conductive feature of the first interconnect structure.

4. The semiconductor structure of claim 1 further comprising a semiconductor package attached to the first redistribution structure opposite the first local interconnect component, the semiconductor package being coupled to the first redistribution structure by a plurality of conductive connectors.

5. The semiconductor structure of claim 4 , wherein the semiconductor package is a core substrate.

6. The semiconductor structure of claim 4 , wherein the semiconductor package is electrically coupled to the first interconnect structure through the first local interconnect component.

7. The semiconductor structure of claim 1 , wherein the conductive through via comprises a first metal pillar, the first metal pillar physically contacting a bottom surface of the first interconnect structure, sidewalls of the first metal pillar being covered by the encapsulant.

8. The semiconductor structure of claim 1 , wherein the first conductive connector of the first local interconnect component comprises a metal pillar.

9. The semiconductor structure of claim 8 , an underfill material, different than the encapsulant material, surrounding the first conductive connector of the first local interconnect component.

10. A semiconductor device, comprising:

a back-side redistribution structure, the back-side redistribution structure comprising a first metallization pattern and a first dielectric layer;

a first local interconnect component including a stack of dielectric layers, respective dielectric layers having embedded therein at least one conductor with a vertically extending longitudinal axis and at least one conductor with a horizontally extending longitudinal axis, a bottom side of the first local interconnect component being attached to a top side of the back-side redistribution structure, a first plurality of conductive features being on the bottom side of the first local interconnect component, the first plurality of conductive features being physically contacting and forming respective direct solderless bonds to the first metallization pattern;

a first encapsulant on the back-side redistribution structure, the first encapsulant covering sidewalls of the first local interconnect component;

a conductive via extending through the first encapsulant, the conductive via having a topmost surface that is planar with a topmost surface of a topmost dielectric layer of the stack of dielectric layers and planar with a topmost surface of the first encapsulant, and having a bottommost surface that is below a topmost surface of the back-side redistribution structure and above a bottommost surface of the back-side redistribution structure;

a first integrated circuit die on the first encapsulant, the first integrated circuit die over a first portion of the first local interconnect component, the first integrated circuit die being electrically coupled to the first local interconnect component; and

a second integrated circuit die on the first encapsulant, the second integrated circuit die over a second portion of the first local interconnect component, the second integrated circuit die being electrically coupled to the first integrated circuit die through the first local interconnect component.

11. The semiconductor device of claim 10 further comprising a second encapsulant encapsulating the first integrated circuit die and the second integrated circuit die.

12. The semiconductor device of claim 10 further comprising an interconnect structure over the first local interconnect component and the first encapsulant, the first integrated circuit die and the second integrated circuit die attached to the interconnect structure opposite the first local interconnect component.

13. The semiconductor device of claim 12 further comprising a third integrated circuit die attached to the interconnect structure neighboring the first integrated circuit die.

14. The semiconductor device of claim 13 further comprising a second local interconnect component, a bottom side of the second local interconnect component being attached to a top side of the back-side redistribution structure, the first encapsulant covering sidewalls of the second local interconnect component, a first portion of the second local interconnect component being under the first integrated circuit die, a second portion of the second local interconnect component being under the third integrated circuit die.

15. The semiconductor device of claim 14 further comprising the third integrated circuit die being electrically coupled to the first integrated circuit die through the second local interconnect component.

16. The semiconductor device of claim 15 further comprising a semiconductor package attached to the back-side redistribution structure opposite the interconnect structure, the second integrated circuit die being electrically coupled to the semiconductor package through the first local interconnect component, the third integrated circuit die being electrically coupled to the semiconductor package through the second local interconnect component.

17. A semiconductor device, comprising:

a local interconnect structure comprising:

a first plurality of dielectric layers, each dielectric layer having embedded therein at least one conductor with a vertically extending longitudinal axis and at least one conductor with a horizontally extending longitudinal axis; and

a first encapsulant, the first encapsulant encapsulating the local interconnect structure, wherein a topmost surface of the first encapsulant is planar with a topmost surface of a topmost surface of the first plurality of dielectric layers;

a first plurality of connectors on the first plurality of dielectric layers, the first plurality of connectors having a bottommost surface that is above a topmost surface of the encapsulant;

a first redistribution structure on a first side of the local interconnect structure and the first encapsulant, the first redistribution structure attached to a first substrate opposite the local interconnect structure, and directly bonded to the local interconnect structure without an intervening layer and without solder;

a second redistribution structure on a second side of the local interconnect structure and the first encapsulant, the second side being opposite the first side;

a first integrated circuit die attached to the second redistribution structure; and

a second integrated circuit die attached to the second redistribution structure, the first integrated circuit die being electrically coupled to the second integrated circuit die through the local interconnect structure.

18. The semiconductor device of claim 17 , wherein the first plurality of connectors are metal pillars.

19. The semiconductor device of claim 17 , further comprising a semiconductor package attached to the first redistribution structure opposite the second redistribution structure, the semiconductor package being electrically coupled to the local interconnect structure through the first redistribution structure.