Semiconductor package

1. A semiconductor package, comprising:

a first redistribution substrate;

a first semiconductor chip disposed on the first redistribution substrate;

a first mold layer that covers the first semiconductor chip and the first redistribution substrate;

a second redistribution substrate disposed on the first mold layer;

a second semiconductor chip disposed on the second redistribution substrate, wherein the second semiconductor chip includes

a second-chip first conductive bump that does not overlap the first semiconductor chip,

a first sidewall that overlaps the first semiconductor chip, and

a second sidewall that does not overlap the first semiconductor chip,

wherein the first sidewall and the second sidewall are opposite to each other; and

a first mold via that penetrates the first mold layer and connects the second-chip first conductive bump to the first redistribution substrate,

wherein the first mold via overlaps the second-chip first conductive bump.

2. The semiconductor package of claim 1 , wherein

the first redistribution substrate includes a first via structure connected to the first mold via,

the second redistribution substrate includes a second via structure connected to the second-chip first conductive bump, and

the second-chip first conductive bump, the second via structure, the first mold via, and the first via structure are vertically aligned with each other.

3. The semiconductor package of claim 2 , wherein each of the first via structure and the second via structure includes a plurality of stacked vias.

4. The semiconductor package of claim 1 , further comprising:

a dummy semiconductor chip disposed on the second redistribution substrate and adjacent to the first sidewall of the second semiconductor chip, wherein the dummy semiconductor chip overlaps the first semiconductor chip; and

an adhesive layer interposed between the dummy semiconductor chip and the second redistribution substrate.

5. The semiconductor package of claim 4 , wherein the dummy semiconductor chip includes silicon and is not electrically connected to the second redistribution substrate.

6. The semiconductor package of claim 1 , wherein

the first semiconductor chip includes a first-chip first conductive bump and a first-chip second conductive bump that are spaced apart from each other, and

the first redistribution substrate includes:

a first redistribution pattern that connects the first mold via to the first-chip first conductive bump; and

a via structure connected to the first-chip second conductive bump and spaced apart from the first redistribution pattern, wherein the via structure overlaps the first-chip second conductive bump.

7. The semiconductor package of claim 1 , further comprising:

a second mold layer that covers the second semiconductor chip;

a third redistribution substrate disposed on the second mold layer;

a third semiconductor chip disposed on the third redistribution substrate wherein the third semiconductor Chip includes a third-chip conductive bump;

a second mold via that penetrates the first mold layer and is spaced apart from the first mold via; and

a third mold via that penetrates the second mold layer,

wherein the first to third semiconductor chips are offset from each other in a first direction,

wherein the second mold via and the third mold via are connected to the third-chip conductive bump, and

wherein the third-chip conductive bump, the third mold via, and the second mold via are vertically aligned with each other.

8. The semiconductor package of claim 1 , further comprising a second mold via spaced apart from the first mold via, wherein the second mold via penetrates the first mold layer at a location that does not overlap either of the first semiconductor chip or the second semiconductor chip,

wherein the second semiconductor chip has a second-chip second conductive bump and a second-chip third conductive bump that are spaced apart from the second-chip first conductive bump, and

wherein the second redistribution substrate includes a redistribution pattern that connects the second-chip first conductive bump and the second-chip second conductive bump to the second mold via.

9. The semiconductor package of claim 1 , further comprising:

a third semiconductor chip disposed on the second redistribution substrate and that is spaced apart from the second semiconductor chip; and

a second mold via that penetrates the first mold layer and connects the third semiconductor chip to the first redistribution substrate,

wherein the third semiconductor chip includes a third-chip conductive bump that does not overlap the first semiconductor chip, and

wherein the third-chip conductive bump overlaps the second mold via.

10. The semiconductor package of claim 1 , further comprising:

a third semiconductor chip disposed on the second redistribution substrate and at a side of the second semiconductor chip;

a fourth semiconductor chip on the first redistribution substrate and at a side of the first semiconductor chip; and

a second mold via that penetrates the first mold layer and connects the third semiconductor chip to the first redistribution substrate,

wherein the third semiconductor chip includes a third-chip conductive bump connected to the second mold via, and

wherein the second mold via and the third-chip conductive bump are vertically aligned with each other.

11. The semiconductor package of claim 1 , further comprising a second mold via that penetrates the first mold layer and is spaced apart from the first mold via,

wherein the second semiconductor chip further includes a second-chip second conductive bump that does not overlap the first semiconductor chip, wherein the second-chip second conductive bump is spaced apart from the second-chip first conductive bump and connected to the second mold via, and

wherein the first redistribution substrate includes a redistribution pattern that connects the first mold via to the second mold via.

12. A semiconductor package, comprising:

a first redistribution substrate;

a first semiconductor chip disposed on the first redistribution substrate;

a first mold layer that covers the first semiconductor chip and the first redistribution substrate;

a second redistribution substrate disposed on the first mold layer;

a second semiconductor chip disposed on the second redistribution substrate, wherein a portion of the second semiconductor chip overlaps a portion of the first semiconductor chip;

a first mold via at a side of the first semiconductor chip, wherein the first mold via penetrates the first mold layer and overlaps the second semiconductor chip; and

a second mold via spaced apart from the first mold via, wherein the second mold via penetrates the first mold layer at a location that does not overlap either of the first semiconductor chip or the second semiconductor chip,

wherein the second semiconductor chip includes:

a second-chip first conductive bump that does not overlap the first semiconductor chip and is connected to the first mold via; and

a second-chip second conductive bump that overlaps the first semiconductor chip and is connected to the second mold via,

wherein the first mold via overlaps the second-chip first conductive bump,

wherein the second redistribution substrate includes a redistribution pattern that connects the second-chip second conductive bump to the second mold via, wherein the second semiconductor chip has a first width in a first direction,

wherein a portion of the second semiconductor chip has a second width in the first direction, the portion of the second semiconductor chip overlapping the first semiconductor chip, and

wherein the second width is about 10% to about 90% of the first width.

13. The semiconductor package of claim 12 , wherein

the first redistribution substrate includes a first via structure connected to the first mold via,

the second redistribution substrate includes a second via structure connected to the second-chip first conductive bump, and

the second-chip first conductive bump, the second via structure, the first mold via, and the first via structure are vertically aligned with each other.

14. The semiconductor package of claim 13 , further comprising a solder ball bonded to the first redistribution substrate and connected to the first via structure,

wherein the first redistribution substrate further includes an under-bump between the first via structure and the solder ball, and

the first via structure, the under-hump, and the solder ball are vertically aligned with each other.

15. The semiconductor package of claim 12 , further comprising:

a dummy semiconductor chip disposed on the second redistribution substrate and adjacent to one sidewall of the second semiconductor chip, wherein the dummy semiconductor chip overlaps the first semiconductor chip; and

an adhesive layer interposed between the dummy semiconductor chip and the second redistribution substrate.

16. The semiconductor package of claim 12 , wherein the second semiconductor chip has a first width in a first direction,

wherein the portion of the second semiconductor chip that overlaps the portion of the first semiconductor chip has a second width in the first direction, and

wherein the second width ranges from about 10% to about 90% of the first width.

17. A semiconductor package, comprising;

a first redistribution substrate, a first semiconductor chip, a second redistribution substrate, a second semiconductor chip, a third redistribution substrate, and a third semiconductor chip that are sequentially stacked;

a first mold layer interposed between the first redistribution substrate and the second redistribution substrate;

a second mold layer interposed between the second redistribution substrate and the third redistribution substrate;

a first mold via and a second mold via that penetrate the first mold layer and are spaced apart from each other; and

a third mold via that penetrates the second mold layer,

wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are offset from each other in a first direction,

wherein the second semiconductor chip is connected through the first mold via to the first redistribution substrate, and

wherein the third semiconductor chip is connected to the first redistribution substrate through the third mold via and the second mold via, wherein the third mold via and the second mold via are vertically aligned with each other.

18. The semiconductor package of claim 17 ,

wherein the second semiconductor chip includes a second-chip conductive bump connected to the first mold via, and

wherein the second-chip conductive bump and the first mold via are vertically aligned with each other.

19. The semiconductor package of claim 17 ,

wherein the third semiconductor chip includes a third-chip conductive bump connected to the third mold via,

wherein the second mold via, the third mold via, and the third-chip conductive bump are vertically aligned with each other.

20. The semiconductor package of claim 17 , wherein

the first redistribution substrate includes a redistribution pattern that connects the first mold via to the second mold via, and

the third semiconductor chip is electrically connected to the second semiconductor chip through the third mold via, the second mold via, the redistribution pattern, and the first mold via.