Semiconductor package including neighboring die contact and seal ring structures, and methods for forming the same

1. A semiconductor package comprising:

a first die;

a second die stacked on an upper surface of the first die, the second die comprising a second semiconductor substrate and a second seal ring structure that extends along a perimeter of the second semiconductor substrate;

a third die stacked on the upper surface of the first die, the third die comprising a third semiconductor substrate and a third seal ring structure that extends along a perimeter of the third semiconductor substrate; and

a connection circuit that extends through the second seal ring structure and the third seal ring structure, in a lateral direction perpendicular to a stacking direction of the first die and the second die, to electrically connect the second semiconductor substrate and the third semiconductor substrate.

2. The semiconductor package of claim 1 , wherein the connection circuit comprises a connection line that extends from an upper surface of the second die to an upper surface of the third die.

3. The semiconductor package of claim 2 , wherein:

the second die comprises a second interconnect structure and a second dielectric structure in which the second interconnect structure and the second seal ring structure are disposed;

the third die comprises a third interconnect structure and a third dielectric structure in which the third interconnect structure and the third seal ring structure are disposed; and

the connection circuit comprises a portion of the second interconnect structure that extends through the second seal ring structure and contacts the connection line and a portion of the third interconnect structure that extends through the third seal ring structure and contacts the connection line.

4. The semiconductor package of claim 3 , wherein the second seal ring structure comprises:

a second seal ring that surrounds the second interconnect structure; and

a second circuit seal that extends from the second seal ring, around the portion of the second interconnect structure, and back to the second seal ring.

5. The semiconductor package of claim 4 , wherein the portion of the second interconnect structure extends under the second circuit seal, between the second circuit seal and the second seal ring, and over the second seal ring, to electrically connect the connection line and the second semiconductor substrate.

6. The semiconductor package of claim 4 , wherein the third seal ring structure comprises:

a third seal ring that surrounds the third interconnect structure; and

a third circuit seal that extends from the third seal ring, around the portion of the third interconnect structure, and back to the third seal ring.

7. The semiconductor package of claim 6 , wherein the portion of the third interconnect structure extends under the third circuit seal, between the third circuit seal and the third seal ring, and over the third seal ring, to electrically connect the connection line and the third semiconductor substrate.

8. The semiconductor package of claim 4 , further comprising barrier layers disposed around the second interconnect structure, the third interconnect structure, the second seal ring structure, and the third seal ring structure.

9. The semiconductor package of claim 4 , wherein the second seal ring structure is electrically grounded to a first semiconductor substrate of the first die.

10. The semiconductor package of claim 9 , wherein the second die comprises a second through-substrate via (TSV) structure that extends through the second semiconductor substrate and that electrically connects the second seal ring structure to the first die.

11. The semiconductor package of claim 10 , wherein:

the TSV is electrically connected to a first interconnect structure disposed on a first semiconductor substrate of the first die, by a die bonding pad; and

a first seal ring of the first die is electrically connected to the bonding pad by a pad extension, such that the second seal ring structure and the first seal ring are both electrically grounded to the first semiconductor substrate by the first interconnect structure.

12. The semiconductor package of claim 1 , wherein a connection line is disposed in a passivation layer that covers the upper surface of the second die and the upper surface of the third die.

13. The semiconductor package of claim 1 , wherein the second semiconductor die and the third semiconductor die are separated by a minimum distance of at least one micron.

14. A semiconductor package comprising:

a first die;

a second die stacked on an upper surface of the first die, the second die comprising a second semiconductor substrate, a second dielectric structure disposed on the second semiconductor substrate, a second interconnect structure disposed in the second dielectric structure, and a second seal ring structure disposed in the second dielectric structure;

a third die stacked on the upper surface of the first die and separated from the second die in a lateral direction perpendicular to a vertical direction, the third die comprising a third semiconductor substrate, a third dielectric structure disposed on the third semiconductor substrate, a third interconnect structure disposed in the third dielectric structure, and a third seal ring structure disposed in the third dielectric structure; and

a die connection line extending from an upper surface of the second die to an upper surface of the third die to electrically connect a portion of the second interconnect structure that extends through the second seal ring structure, in the lateral direction, to a portion of the third interconnect structure that extends through the third seal ring structure, in the lateral direction.

15. The semiconductor package of claim 14 , wherein the second seal ring structure comprises:

a second seal ring that at least partially surrounds the second interconnect structure;

an inner second circuit seal that extends from the second seal ring, around a portion of the second interconnect structure, and back to the second seal ring; and

an outer second circuit seal that extends from the second seal ring, around the inner second circuit seal, and back to the second seal ring.

16. The semiconductor package of claim 15 , wherein the third seal ring structure comprises:

a third seal ring that at least partially surrounds the third interconnect structure;

a third circuit seal that extends from the third seal ring, around a portion of the third interconnect structure, and back to the third seal ring; and

a fourth seal ring that extends around the third seal ring.

17. The semiconductor package of claim 16 , wherein:

the portion of the second interconnect structure extends under the outer second circuit seal, between the inner second circuit seal and the second seal ring, and over the second seal ring, to electrically connect the second semiconductor substrate and the connection line; and

the portion of the third interconnect structure extends under the third circuit seal, between the third circuit seal and the third seal ring, and over the third seal ring and the fourth seal ring, to electrically connect the third semiconductor substrate and the connection line.

18. The semiconductor package of claim 16 , wherein:

the inner second circuit seal and the outer second circuit seal are separated by a minimum distance of greater than one micron; and

the third seal ring and the fourth seal ring are separated by a minimum distance of greater than one micron.

19. The semiconductor package of claim 15 , wherein:

the second die comprises a second through-substrate via (TSV) structure that extends through the second semiconductor substrate and that electrically connects the second seal ring structure to the first die; and

the third die comprises a third through-substrate via (TSV) structure that extends through the third semiconductor substrate and that electrically connects the third seal ring structure to the first die.

20. A semiconductor package comprising:

a first die;

a second die stacked on an upper surface of the first die, the second die comprising a second semiconductor substrate, a second interconnect structure disposed on an upper surface of the second semiconductor substrate, a second seal ring that surrounds the second interconnect structure, and a second circuit seal that extends from the second seal ring, around a portion of the second interconnect structure, and back to the second seal ring;

a third die stacked on the upper surface of the first die, the third die comprising a third semiconductor substrate, a third interconnect structure disposed on an upper surface of the third semiconductor substrate, a third seal ring that surrounds the third interconnect structure, and a third circuit seal that extends from the third seal ring, around a portion of the third interconnect structure, and back to the third seal ring; and

a die connection line that electrically connects the portion of the second interconnect structure with the portion of the third interconnect structure.