Semiconductor devices and methods of manufacturing thereof
A semiconductor device includes a first silicon layer. The semiconductor device includes a plurality of first buried oxide layers embedded in the first silicon layer. The semiconductor device includes a second silicon layer disposed over the plurality of first buried oxide layers. Vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different.
1. A semiconductor device, comprising:
a first silicon layer;
a plurality of first buried oxide layers embedded in the first silicon layer; and
a second silicon layer disposed over the plurality of first buried oxide layers;
wherein vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different, wherein all of the plurality of first buried oxide layers are separated from one another, and wherein all of the plurality of first buried oxide layers are laterally offset from one another and vertically spaced apart from one another.
2. The semiconductor device of claim 1 , further comprising a shallow trench isolation structure surrounding the first silicon layer, wherein each of the plurality of first buried oxide layers has at least one sidewall in contact with the shallow trench isolation structure.
3. The semiconductor device of claim 1 , further comprising:
a first source/drain structure in the second silicon layer; and
a second source/drain structure in the second silicon layer.
4. The semiconductor device of claim 3 , wherein a topmost one of the plurality of first buried oxide layers is in contact with at least one of the first source/drain structure or second source/drain structure.
5. The semiconductor device of claim 3 , further comprising a gate structure disposed over the second silicon layer and between the first source/drain structure and second source/drain structure.
6. The semiconductor device of claim 5 , wherein a region of the second silicon layer, disposed below the gate structure, is free from being connected to any of the plurality of first buried oxide layers.
7. The semiconductor device of claim 5 , wherein a region of the second silicon layer, disposed below the gate structure, is partially or fully connected to a topmost one of the plurality of first buried oxide layers.
8. The semiconductor device of claim 1 , wherein the second silicon layer is an epitaxial layer.
9. The semiconductor device of claim 1 , further comprising at least one second buried oxide layer embedded in the second silicon layer.
10. A semiconductor device, comprising:
a first silicon layer;
a plurality of buried oxide layers embedded in the first silicon layer;
a second silicon layer disposed over the plurality of buried oxide layers; and
a first and a second source/drain structures disposed in the second silicon layer,
wherein a topmost one of the plurality of buried oxide layers is in contact with at least one of the first and the second source/drain structures, and wherein all of the plurality of buried oxide layers are laterally offset from one another and vertically spaced apart from one another.
11. The semiconductor device of claim 10 , further comprising:
a gate structure disposed over the second silicon layer and between the first source/drain structure and second source/drain structure.
12. The semiconductor device of claim 10 , wherein vertical distances between the plurality of buried oxide layers and the second silicon layer, respectively, are different.
13. The semiconductor device of claim 10 , wherein the second silicon layer includes an epitaxial layer.
14. The semiconductor device of claim 10 , wherein a region of the second silicon layer is free from being connected to any of the plurality of buried oxide layers.
15. The semiconductor device of claim 10 , further comprising:
a shallow trench isolation (STI) structure surrounding the first and the second silicon layers, wherein at least one of the plurality of buried oxide layers has at least one sidewall in contact with the STI structure.
16. A semiconductor device, comprising:
a first silicon layer;
a plurality of buried oxide layers embedded in the first silicon layer;
a second silicon layer disposed over the plurality of buried oxide layers; and
wherein a region of the second silicon layer is free from being connected to any of the plurality of buried oxide layers, wherein all of the plurality of buried oxide layers are separated from one another, and wherein all of the plurality of buried oxide layers are laterally offset from one another and vertically spaced apart from one another.
17. The semiconductor device of claim 16 , wherein vertical distances between the plurality of buried oxide layers and the second silicon layer, respectively, are different.
18. The semiconductor device of claim 16 , wherein the second silicon layer includes an epitaxial layer.
19. The semiconductor device of claim 16 , further comprising:
a shallow trench isolation (STI) structure surrounding the first and the second silicon layers, wherein at least one of the plurality of buried oxide layers has at least one sidewall in contact with the STI structure.
20. The semiconductor device of claim 16 , further comprising:
a gate structure disposed over the second silicon layer and between a first source/drain structure and a second source/drain structure.