Common-mode current removal scheme for digital-to-analog converters

1. A digital-to-analog converter (DAC) circuit comprising:

a plurality of current-steering cells;

a resistor ladder circuit coupled to the plurality of current-steering cells;

a first current sink coupled between a shunt branch of the resistor ladder circuit and a reference potential node for the DAC circuit, wherein the first current sink is configured to sink a first portion of a common-mode current of the DAC circuit; and

a second current sink coupled between a first output of the DAC circuit and the reference potential node, wherein the second current sink is configured to sink a second portion of the common-mode current of the DAC circuit.

2. The DAC circuit of claim 1 , wherein the first current sink is configured such that the first portion of the common-mode current decreases with an increase in a resistance of the resistor ladder circuit and wherein the second current sink is configured such that the second portion of the common-mode current increases with the increase in the resistance of the resistor ladder circuit.

3. The DAC circuit of claim 1 , wherein the second current sink is configured such that the second portion of the common-mode current counteracts at least a portion of a variation in the first portion of the common-mode current, due to at least one of a process, voltage, or temperature variation in the DAC circuit.

4. The DAC circuit of claim 1 , further comprising a third current sink coupled between a second output of the DAC circuit and the reference potential node for the DAC circuit, wherein the first output and the second output compose a differential output of the DAC circuit.

5. The DAC circuit of claim 1 , wherein the first current sink is coupled between a center of the shunt branch in a segment of the resistor ladder circuit and the reference potential node for the DAC circuit.

6. The DAC circuit of claim 1 , wherein the first current sink is coupled between the reference potential node and a node between two shunt resistive elements in the shunt branch of the resistor ladder circuit.

7. The DAC circuit of claim 1 , wherein the first current sink is a short between the shunt branch of the resistor ladder circuit and the reference potential node for the DAC circuit.

8. The DAC circuit of claim 1 , wherein the second current sink comprises:

a first current source;

a first current mirror having a first branch coupled to the first current source and having a second branch coupled to a common node;

a second current source;

a second current mirror having a first branch coupled to the second current source and having a second branch coupled to the common node; and

a third current mirror having a first branch coupled to the common node and having a second branch coupled to the first output of the DAC circuit.

9. A digital-to-analog converter (DAC) circuit comprising:

a plurality of current-steering cells;

a resistor ladder circuit coupled to the plurality of current-steering cells;

a first current sink coupled between a shunt branch of the resistor ladder circuit and a reference potential node for the DAC circuit; and

a second current sink coupled between a first output of the DAC circuit and the reference potential node, wherein the second current sink comprises:

a first current source;

a first current mirror having a first branch coupled to the first current source and having a second branch coupled to a common node;

a second current source;

a second current mirror having a first branch coupled to the second current source and having a second branch coupled to the common node; and

a third current mirror having a first branch coupled to the common node and having a second branch coupled to the first output of the DAC circuit.

10. The DAC circuit of claim 9 , wherein the third current mirror has a gain from the first branch of the third current mirror to the second branch of the third current mirror.

11. The DAC circuit of claim 9 , wherein the first current source comprises:

a reference resistive element;

a first transistor;

an amplifier having a first input coupled to a reference voltage source, having a second input coupled to a drain of the first transistor, and having an output coupled to a gate of the first transistor; and

a second transistor having a gate coupled to the output of the amplifier and having a drain coupled the first branch of the first current mirror.

12. The DAC circuit of claim 11 , wherein the reference resistive element is a same resistor type as a plurality of resistive elements in the resistor ladder circuit.

13. The DAC circuit of claim 9 , wherein the second current source is calibrated and is independent of process, voltage, and temperature variation.

14. A method of operating a digital-to-analog converter (DAC) circuit comprising a plurality of current-steering cells and a resistor ladder circuit coupled to the plurality of current-steering cells, the method comprising:

sinking a first portion of a common-mode current of the DAC circuit from a shunt branch of the resistor ladder circuit, wherein the first portion of the common-mode current decreases with an increase in a resistance of the resistor ladder circuit; and

sinking a second portion of the common-mode current of the DAC circuit from a first output of the DAC circuit, wherein the second portion of the common-mode current increases with the increase in the resistance of the resistor ladder circuit.

15. The method of claim 14 , wherein the second portion of the common-mode current counteracts at least a portion of a variation in the first portion of the common-mode current, due to at least one of a process, voltage, or temperature variation in the DAC circuit.

16. The method of claim 14 , further comprising sinking a third portion of the common-mode current of the DAC circuit from a second output of the DAC circuit, wherein the first output and the second output compose a differential output of the DAC circuit.

17. The method of claim 14 , wherein sinking the second portion of the common-mode current comprises:

generating a first reference current;

generating a second reference current in a first branch of a first current mirror based on the generating of the first reference current;

mirroring the second reference current in a second branch of the first current mirror;

generating a third reference current in a first branch of a second current mirror;

mirroring the third reference current in a second branch of the second current mirror;

providing a difference current, as a difference between the mirrored third reference current and the mirrored second reference current, to a first branch of a third current mirror; and

mirroring the difference current in a second branch of the third current mirror, wherein the second portion of the common-mode current comprises the mirrored difference current.

18. The method of claim 17 , wherein mirroring the difference current comprises mirroring the difference current with a gain from the first branch of the third current mirror to the second branch of the third current mirror.

19. The method of claim 17 , wherein the third reference current is calibrated and is independent of process, voltage, and temperature variation.

20. The DAC circuit of claim 8 , wherein the third current mirror has a gain from the first branch of the third current mirror to the second branch of the third current mirror.