Equalizer circuit and related power management circuit
An equalizer circuit and related power management circuit are provided. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit(s) via a signal path for amplifying a radio frequency signal(s). An equalizer circuit is provided in the power management circuit to equalize the differential target voltage prior to generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function including a second-order complex-zero term and a real-zero term for offsetting a transfer function of an inherent trace inductance of the signal path and an inherent impedance of the voltage amplifier circuit. By employing the second-order transfer function with the real-zero term, it is possible to reduce distortion in the ET voltage, especially when the RF signal(s) is modulated in a wide modulation bandwidth.
1. An equalizer circuit comprising:
a voltage input that receives a differential target voltage comprising a negative target voltage and a positive target voltage;
a voltage output that outputs an equalized target voltage corresponding to the differential target voltage; and
an equalizer tuning circuit coupled between the voltage input and the voltage output and configured to cause the equalized target voltage to be generated from the differential target voltage based on a transfer function comprising a second-order complex-zero term and a real-zero term.
2. The equalizer circuit of claim 1 , wherein the equalizer tuning circuit comprises:
a left resistor and a right resistor coupled in series between the voltage input and the voltage output; and
a tunable capacitor provided between a ground and a coupling node in between the left resistor and the right resistor.
3. The equalizer circuit of claim 2 , wherein the equalizer tuning circuit further comprises a shunt resistor coupled between the tunable capacitor and the ground.
4. The equalizer circuit of claim 2 , further comprising a control circuit configured to adjust the tunable capacitor based on the differential target voltage to thereby adjust the real-zero term in the transfer function.
5. The equalizer circuit of claim 4 , wherein the control circuit is further configured to:
retrieve a capacitance from a lookup table (LUT) based on a modulation bandwidth indicated by the differential target voltage; and
set the tunable capacitor to the capacitance retrieved from the LUT.
6. The equalizer circuit of claim 2 , further comprising a first operational amplifier and a second operational amplifier coupled in series between the voltage input and the voltage output.
7. The equalizer circuit of claim 6 , wherein the voltage input comprises a positive target voltage input that receives the positive target voltage and a negative target voltage input that receives the negative target voltage.
8. The equalizer circuit of claim 7 , wherein:
the first operational amplifier comprises:
a first inverting input node coupled to the positive target voltage input;
a first non-inverting input node coupled to the ground; and
a first output node; and
the second operational amplifier comprises:
a second inverting input node coupled to the first output node and the negative target voltage input;
a non-inverting input node coupled to the ground; and
a second output node coupled to the voltage output.
9. The equalizer circuit of claim 8 , wherein the equalizer tuning circuit further comprises:
a left node coupled to the second inverting input node of the second operational amplifier and to the negative target voltage input; and
a right node coupled to the voltage output;
wherein the left resistor and the right resistor are coupled in series between the left node and the right node.
10. A power management circuit comprising:
an equalizer circuit comprising:
a voltage input that receives a differential target voltage comprising a negative target voltage and a positive target voltage;
a voltage output that outputs an equalized target voltage corresponding to the differential target voltage; and
an equalizer tuning circuit coupled between the voltage input and the voltage output and configured to cause the equalized target voltage to be generated from the differential target voltage based on a transfer function comprising a second-order complex-zero term and a real-zero term; and
a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on the equalized target voltage.
11. The power management circuit of claim 10 , wherein the equalizer tuning circuit comprises:
a left resistor and a right resistor coupled in series between the voltage input and the voltage output; and
a tunable capacitor having a first end coupled to a coupling node located between the left resistor and the right resistor and a second end coupled to a ground.
12. The power management circuit of claim 11 , wherein the equalizer tuning circuit further comprises a shunt resistor coupled between the second end of the tunable capacitor and the ground.
13. The power management circuit of claim 11 , wherein the equalizer circuit further comprises a control circuit configured to adjust the tunable capacitor based on the differential target voltage to thereby adjust the real-zero term in the transfer function.
14. The power management circuit of claim 13 , wherein the control circuit is further configured to:
retrieve a capacitance from a lookup table (LUT) based on a modulation bandwidth indicated by the differential target voltage; and
set the tunable capacitor to the capacitance retrieved from the LUT.
15. The power management circuit of claim 11 , wherein the equalizer circuit further comprises a first operational amplifier and a second operational amplifier coupled in series between the voltage input and the voltage output.
16. The power management circuit of claim 15 , wherein the voltage input comprises a positive target voltage input that receives the positive target voltage and a negative target voltage input that receives the negative target voltage.
17. The power management circuit of claim 16 , wherein:
the first operational amplifier comprises:
a first inverting input node coupled to the positive target voltage input;
a first non-inverting input node coupled to the ground; and
a first output node; and
the second operational amplifier comprises:
a second inverting input node coupled to the first output node and the negative target voltage input;
a non-inverting input node coupled to the ground; and
a second output node coupled to the voltage output.
18. The power management circuit of claim 17 , wherein the equalizer tuning circuit further comprises:
a left node coupled to the second inverting input node of the second operational amplifier and to the negative target voltage input; and
a right node coupled to the voltage output;
wherein the left resistor and the right resistor are coupled in series between the left node and the right node.
19. The power management circuit of claim 10 , wherein the voltage amplifier circuit comprises:
a voltage amplifier configured to generate an initial ET voltage based on the equalized target voltage; and
an offset capacitor configured to raise the initial ET voltage by an offset voltage to generate the ET voltage.
20. The power management circuit of claim 10 , further comprising:
a multi-level charge pump configured to generate a low-frequency voltage at a plurality of voltage levels based on a battery voltage; and
a power inductor configured to induce a low-frequency current based on the low-frequency voltage.