Virtual radio frequency (VRF) equalizer for envelope tracking integrated circuit (ETIC)
A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device.
1. An envelope tracking integrated circuit (ETIC) comprising:
a circuit configured to implement a first transform function to cancel ripple induced in a load-modulated power amplifier stage, wherein the circuit is further configured to use a time delay (τ) in calculating a ripple cancelation;
a parallel amplifier coupled to the circuit; and
a second circuit configured to compensate for a pole introduced by the parallel amplifier.
2. The ETIC of claim 1 , wherein the circuit further comprises a look-up table (LUT) that uses a Vcc target to determine an output current Icc.
3. The ETIC of claim 2 , wherein the circuit further comprises a second transform function coupled to the LUT and configured to take a derivative of an output of the LUT using a Laplace transformation.
4. The ETIC of claim 1 , wherein the circuit is configured to calculate a new effective capacitance (CPA new ) for the load-modulated power amplifier stage based on the time delay.
5. An envelope tracking integrated circuit (ETIC) comprising:
a circuit configured to implement a first transform function to cancel ripple induced in a load-modulated power amplifier stage;
a parallel amplifier coupled to the circuit; and
a second circuit configured to compensate for a pole introduced by the parallel amplifier.
6. The ETIC of claim 5 , wherein the circuit comprises a first operational amplifier (op-amp).
7. The ETIC of claim 6 , wherein the circuit further comprises a second op-amp serially coupled to the first op-amp through a capacitor.
8. The ETIC of claim 6 , wherein the circuit further comprises a T-network feedback loop associated with the first op-amp.
9. The ETIC of claim 8 , wherein the T-network feedback loop comprises a first resistor serially coupled to a second resistor with a node therebetween, wherein the node is coupled to ground through a capacitor.
10. The ETIC of claim 6 , wherein the circuit further comprises an input coupled to the first op-amp through a variable capacitor.
11. The ETIC of claim 10 , wherein the circuit further comprises a resistor coupled electrically to the variable capacitor and electrically parallel thereto.
12. The ETIC of claim 6 , wherein the circuit further comprises an input coupled to the first op-amp through a variable resistor.
13. The ETIC of claim 12 , wherein the circuit further comprises a capacitor coupled electrically to the variable resistor and electrically parallel thereto.
14. The ETIC of claim 1 , further comprising an anti-aliasing filter (AAF) coupled to the circuit and the parallel amplifier and positioned between the circuit and the parallel amplifier.
15. The ETIC of claim 6 , further comprising:
a T-network feedback loop associated with the first op-amp; and
wherein the circuit further comprises a second op-amp serially coupled to the first op-amp through a capacitor.
16. The ETIC of claim 10 , wherein the variable capacitor is configured to vary capacitance as a function of a non-linear input voltage.
17. The ETIC of claim 12 , wherein the variable resistor is configured to vary resistance as a function of a non-linear input voltage.