Dynamic random access memory (DRAM) row hammering mitigation
An effect known as “rowhammer” may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window may be counted and compared with a threshold. When it is detected that the number of row activation commands within the refresh window exceeds the threshold, an additional refresh command may be provided to the DRAM.
1. A method, comprising:
detecting row activation commands directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of the DRAM array;
counting a first number of the row activation commands occurring within a window between a first refresh command and a second refresh command;
comparing the first number of row activation commands with a first threshold, the first threshold comprising a predetermined number associated with refresh operations required to refresh all rows of a bank; and
providing an additional refresh command to the DRAM array within the window in response to detecting the first number of row activation commands exceeds the first threshold.
2. The method of claim 1 , wherein a plurality of rows of each sub-bank overlap with a plurality of rows of another sub-bank.
3. The method of claim 2 , wherein at least 16 rows of each sub-bank overlap with at least 16 rows of another sub-bank.
4. The method of claim 1 , wherein the first and second refresh commands are consecutive.
5. The method of claim 1 , further comprising increasing a timing gap between successive commands provided to the DRAM array in response to detecting the first number of row activation commands exceeds the first threshold.
6. The method of claim 5 , further comprising, after increasing the timing gap:
counting a second number of row activation commands occurring within the window;
comparing a sum of the first and second number of row activation commands with a second threshold; and
further increasing the timing gap between successive commands provided to the DRAM array in response to detecting the sum of the first and second number of row activation commands exceeds the second threshold.
7. The method of claim 1 , further comprising hashing an original row address associated with each row activation command, and providing a hashed row address in association with the row activation command to the DRAM array instead of the original row address.
8. A system, comprising:
command detection logic configured to detect row activation commands directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array;
activation command counting logic configured to count a first number of the row activation commands occurring within a window between a first refresh command and a second refresh command, and configured to compare the first number of row activation commands with a first threshold, the first threshold comprising a predetermined number associated with refresh operations required to refresh all rows of a bank; and
an additional refresh command generator configured to provide an additional refresh command to the DRAM array within the window in response to detecting the first number of row activation commands exceeds the first threshold.
9. The system of claim 8 , wherein a plurality of rows of each sub-bank overlap with a plurality of rows of another sub-bank.
10. The system of claim 9 , wherein at least 16 rows of each sub-bank overlap with at least 16 rows of another sub-bank.
11. The system of claim 8 , wherein the first and second refresh commands are consecutive.
12. The system of claim 8 , further comprising a timing controller configured to increase a timing gap between successive commands provided to the DRAM array in response to detecting the first number of row activation commands exceeds the first threshold.
13. The system of claim 12 , wherein:
the activation command counting logic is further configured to, after the timing gap is increased, count a second number of row activation commands occurring within the window; and
the timing controller is further configured to compare a sum of the first and second number of row activation commands with a second threshold and to further increase the timing gap between successive commands provided to the DRAM array in response to detecting the sum of the first and second number of row activation commands exceeds the second threshold.
14. The system of claim 8 , further comprising row address hashing logic configured to hash an original row address associated with each row activation command, and provide a hashed row address in association with the row activation command to the DRAM array instead of the original row address.
15. A system, comprising:
means for detecting row activation commands directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of the DRAM array;
means for counting a first number of the row activation commands occurring within a window between a first refresh command and a second refresh command and for comparing the first number of row activation commands with a first threshold the first threshold comprising a predetermined number associated with refresh operations required to refresh all rows of a bank; and
means for providing an additional refresh command to the DRAM array within the window in response to detecting the first number of row activation commands exceeds the first threshold.
16. The system of claim 15 , wherein a plurality of rows of each sub-bank overlap with a plurality of rows of another sub-bank.
17. The system of claim 16 , wherein at least 16 rows of each sub-bank overlap with at least 16 rows of another sub-bank.
18. The system of claim 15 , wherein the first and second refresh commands are consecutive.
19. The system of claim 15 , further comprising means for increasing a timing gap between successive commands provided to the DRAM array in response to detecting the first number of row activation commands exceeds the first threshold.
20. The system of claim 19 , further comprising, after increasing the timing gap:
means for counting a second number of row activation commands occurring within the window;
means for comparing a sum of the first and second number of row activation commands with a second threshold; and
means for further increasing the timing gap between successive commands provided to the DRAM array in response to detecting the sum of the first and second number of row activation commands exceeds the second threshold.
21. The system of claim 15 , further comprising means for hashing an original row address associated with each row activation command, and providing a hashed row address in association with the row activation command to the DRAM array instead of the original row address.
22. A memory controller, comprising:
command generator logic configured to generate dynamic random access memory (DRAM) commands in response to memory transaction requests, the DRAM commands including row activation commands and refresh commands;
command detection logic configured to detect row activation commands directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array;
activation command counting logic configured to count a first number of the row activation commands occurring within a window between a first refresh command and a second refresh command, and configured to compare the first number of row activation commands with a first threshold, the first threshold comprising a predetermined number associated with refresh operations required to refresh all rows of a bank; and
an additional refresh command generator configured to provide an additional refresh command to the DRAM array within the window in response to detecting the first number of row activation commands exceeds the first threshold.
23. The memory controller of claim 22 , wherein a plurality of rows of each sub-bank overlap with a plurality of rows of another sub-bank.
24. The memory controller of claim 22 , wherein the first and second refresh commands are consecutive.
25. The memory controller of claim 22 , further comprising a timing controller configured to increase a timing gap between successive commands provided to the DRAM array in response to detecting the first number of row activation commands exceeds the first threshold.
26. The memory controller of claim 22 , further comprising row address hashing logic configured to hash an original row address associated with each row activation command, and provide a hashed row address in association with the row activation command to the DRAM array instead of the original row address.