Row hammer effect mitigation through least row used buffering of writeback data
View Patent ↗Buffering row data from multiple row read operations and delaying writeback of buffered row data to a cell array by writing back data from a least recently used register only when adding new row data would exceed the capacity of the row data buffer structure.
1 . A memory device comprising:
a cell array comprising a plurality of rows for storing data;
sense amplifiers configured to read data from a selected row of the cell array;
a row data buffer structure operatively coupled to the sense amplifiers and the cell array, the row data buffer structure comprising:
a plurality of registers, each register configured to store a row address and corresponding row data read from the cell array;
content addressable memory (CAM) configured to compare a current row address with row addresses stored in the plurality of registers to determine if the corresponding row data is buffered; and
least-recently-used (LRU) logic configured to track usage of the registers and manage storage of new row addresses and row data;
wherein the row data buffer structure is configured to buffer row data from multiple row read operations and to delay writeback of buffered row data to the cell array by writing back data from a least recently used register only when adding new row data would exceed capacity of the row data buffer structure, thereby mitigating row hammer effects through temporal spacing of row activations.
2 . The memory device of claim 1 , wherein the LRU logic is configured to:
store a new row address and corresponding row data in an available register of the plurality of registers when the row data buffer structure is not full; and
upon the buffer reaching capacity, select the least recently used register for writeback to the cell array and replacement with new row data.
3 . The memory device of claim 2 , wherein the row data buffer structure is further configured to:
upon determining a match via the CAM for the current row address during a read or write operation, access or modify the corresponding row data in the matched register without writing back the modified row data to the cell array until that register is selected as least recently used.
4 . The memory device of claim 3 , wherein, upon writing back data from the least recently used register to the cell array, the row data buffer structure is further configured to:
route the row address stored in the least recently used register to a row address decoder of the cell array to select the corresponding row; and
activate row storage drivers to write the row data from the least recently used register back to the selected row in the cell array before storing new row data in that register.
5 . The memory device of claim 4 , wherein a number of the plurality of registers in the row data buffer structure is determined based on an analysis of characteristics of the cell array to achieve a desired delay between writebacks to a same row in the cell array.
6 . The memory device of claim 5 , wherein the row data buffer structure further comprises:
inputs configured to receive row data from the sense amplifiers, the current row address for comparison by the CAM, and modified row data from input/output (I/O) logic; and
wherein, during a write operation to a buffered row, the modified row data from the I/O logic is written back to the matched register in the row data buffer structure without immediate writeback to the cell array.
7 . The memory device of claim 6 , wherein the row data buffer structure further comprises:
outputs configured to provide read data from a matched register to output drivers coupled to memory interface circuits, and to provide row write data and the corresponding row address from the least recently used register to row storage drivers and a row address decoder of the cell array during writeback.
8 . The memory device of claim 1 , wherein the row data buffer structure is initialized in an empty state with no row addresses or row data stored in the plurality of registers, and wherein, upon an initial row read operation where the current row address does not match any stored row addresses via the CAM, the current row address and corresponding row data from the sense amplifiers are stored in an available register of the plurality of registers, and the LRU logic is updated accordingly.
9 . The memory device of claim 1 , wherein the row data buffer structure is configured to:
provide buffered row data from a matched register to column select logic for read operations via memory interface circuits; and
receive updated row data from the column select logic for write operations, wherein the updated row data is stored back in the matched register without immediate writeback to the cell array; and
wherein the LRU logic is implemented in hardware, firmware, or a combination thereof, and is configured to update usage status of each register upon every access, read, or write operation to maintain accurate least-recently-used tracking for writeback and replacement decisions.
10 . A method for mitigating row hammer effects in a memory device having a cell array comprising a plurality of rows for storing data and sense amplifiers configured to read data from a selected row of the cell array, the method comprising:
providing a row data buffer structure operatively coupled to the sense amplifiers and the cell array, the row data buffer structure comprising a plurality of registers, each register configured to store a row address and corresponding row data read from the cell array, content addressable memory (CAM) configured to compare a current row address with row addresses stored in the plurality of registers to determine if the corresponding row data is buffered, and least-recently-used (LRU) logic configured to track usage of the registers and manage storage of new row addresses and row data;
buffering, using the row data buffer structure, row data from multiple row read operations; and
delaying writeback of buffered row data to the cell array by writing back data from a least recently used register only when adding new row data would exceed capacity of the row data buffer structure, thereby mitigating row hammer effects through temporal spacing of row activations.
11 . The method of claim 10 , wherein the LRU logic performs:
storing a new row address and corresponding row data in an available register of the plurality of registers when the row data buffer structure is not full; and
upon the buffer reaching capacity, selecting the least recently used register for writeback to the cell array and replacement with new row data.
12 . The method of claim 11 , further comprising: upon determining a match via the CAM for the current row address during a read or write operation, accessing or modifying the corresponding row data in the matched register without writing back the modified row data to the cell array until that register is selected as least recently used.
13 . The method of claim 12 , wherein, upon writing back data from the least recently used register to the cell array, the method further comprises:
routing the row address stored in the least recently used register to a row address decoder of the cell array to select the corresponding row; and
activating row storage drivers to write the row data from the least recently used register back to the selected row in the cell array before storing new row data in that register.
14 . The method of claim 13 , wherein a number of the plurality of registers in the row data buffer structure is determined based on an analysis of characteristics of the cell array to achieve a desired delay between writebacks to a same row in the cell array.
15 . The method of claim 14 , further comprising:
receiving, at inputs of the row data buffer structure, row data from the sense amplifiers, the current row address for comparison by the CAM, and modified row data from input/output (I/O) logic; and
during a write operation to a buffered row, writing back the modified row data from the I/O logic to the matched register in the row data buffer structure without immediate writeback to the cell array.
16 . The method of claim 15 , further comprising:
providing, from outputs of the row data buffer structure, read data from a matched register to output drivers coupled to memory interface circuits; and
providing row write data and the corresponding row address from the least recently used register to row storage drivers and a row address decoder of the cell array during writeback.
17 . The method of claim 10 , further comprising:
initializing the row data buffer structure in an empty state with no row addresses or row data stored in the plurality of registers; and
upon an initial row read operation where the current row address does not match any stored row addresses via the CAM, storing the current row address and corresponding row data from the sense amplifiers in an available register of the plurality of registers, and updating the LRU logic accordingly.
18 . The method of claim 10 , further comprising:
providing buffered row data from a matched register to column select logic for read operations via memory interface circuits; and
receiving updated row data from the column select logic for write operations, wherein the updated row data is stored back in the matched register without immediate writeback to the cell array.
19 . The method of claim 10 , further comprising, during a row read operation,
comparing the current row address with row addresses stored in the plurality of registers using the CAM;
upon determining no match via the CAM, storing the row data in the row data buffer structure as active row data and updating the LRU logic; and
upon determining a match via the CAM, ignoring the row data in the cell array and using the row data from the matched register as the active row data without modifying contents of the row data buffer structure except for updating the LRU usage status.