Method and apparatus for reducing light leakage at memory nodes in CMOS image sensors

1. A method for forming a semiconductor device, comprising:

depositing an interlayer dielectric (ILD) layer on a substrate, wherein the substrate comprises a plurality of pixels configured in a pixel array, and wherein each of the plurality of pixels comprises a light-sensing region, a charge-storage region, a light-shielding structure, and at least one via contact;

patterning the ILD layer to simultaneously form a first plurality of through-hole openings and a first plurality of shallow-etched regions in the ILD layer; and

depositing a metal layer on the ILD layer to simultaneously form a plurality of via contacts and at least one grounding contact in the first plurality of through-hole openings and a plurality of light-shielding structures in the first plurality of shallow-etched regions,

wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein each of the plurality of light-shielding structures is configured to over the charge-storage region in a pixel in a vertical direction so as to prevent incident light leaking from the light-sensing region to a signal-processing region, and wherein the patterning further comprises:

patterning a photoresist layer to simultaneously form a second plurality of through-hole openings and a second plurality of shallow-etched regions in the photoresist layer; and

etching the ILD layer using the patterned photoresist layer as a hard mask to simultaneously form the first plurality of through-hole openings and the first plurality of shallow-etched regions in the ILD layer.

2. The method of claim 1 , wherein each of the plurality of light-shielding structures comprises tungsten (W) metal and electrically grounded through the at least one grounding contact.

3. The method of claim 1 , wherein a first thickness of each of the plurality of light-shielding structures is at least 150 nanometers, and wherein a second thickness of the ILD layer is at least 330 nanometers.

4. The method of claim 1 , wherein the charge-storage region comprises at least one of the following: at least one transfer gate and a charge-storage node.

5. The method of claim 1 , wherein each of the plurality of light-shielding structures comprises a first surface and a second surface, wherein the first surface is coplanar with the ILD layer, and wherein the second surface comprises a plurality of wrinkles.

6. The method of claim 1 ,

wherein the second plurality of shallow-etched regions in the photoresist layer is formed using an aperture array with a critical dimension equal to or less than 160 nanometers and a pitch size equal to or less than 260 nanometers.

7. A method of forming a semiconductor device, comprising:

forming a plurality of pixels in a substrate, wherein each of the plurality of pixels comprises a light-sensing region, a charge-storage region comprising a transfer gate, a light-shielding structure, and at least one via contacting the transfer gate,

wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to a signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact; and

patterning the ILD layer to simultaneously form a first plurality of through-hole openings and a first plurality of shallow-etched regions in the ILD layer, wherein the patterning comprises:

patterning a photoresist layer to simultaneously form a second plurality of through-hole openings and a second plurality of shallow-etched regions in the photoresist layer; and

etching the ILD layer using the patterned photoresist layer as a hard mask to simultaneously form the first plurality of through-hole openings and the first plurality of shallow-etched regions in the ILD layer.

8. The method of claim 7 , wherein the light-shielding structure comprises a first surface and a second surface, wherein the first surface is coplanar with the ILD layer, and wherein the second surface comprises a plurality of wrinkles.

9. The method of claim 7 , wherein the light-shielding structure comprises tungsten (W) metal and electrically grounded through at least one grounding contact.

10. The method of claim 7 , wherein a first thickness of the light-shielding structure is at least 150 nanometers, and wherein a second thickness of the ILD layer is at least 330 nanometers.

11. The method of claim 7 , wherein the charge-storage region further comprises a charge-storage node.

12. The method of claim 7 , wherein the light-sensing region comprises a complementary metal-oxide-semiconductor (CMOS) photodiode.

13. The method of claim 7 , wherein the at least one via contact is configured to provide electrical contacts to the charge-storage region and is electrically isolated from the light-shielding structure, wherein the at least one via contact comprises W metal.

14. A method of forming a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, comprising:

forming a plurality of pixels configured in a pixel array in a substrate, wherein each of the plurality of pixels comprises:

a light-sensing region;

a charge-storage region formed adjacent to the light-sensing region in a lateral direction;

a light-shielding structure formed over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to a signal-processing region;

a transfer gate formed over the charge-storage region; and

at least one via contact that extends through an interlayer dielectric (ILD) layer to contact a top surface of the transfer gate; and

patterning the ILD layer to simultaneously form a first plurality of through-hole openings and a first plurality of shallow-etched regions in the ILD layer, wherein the patterning comprises:

patterning a photoresist layer to simultaneously form a second plurality of through-hole openings and a second plurality of shallow-etched regions in the photoresist layer; and

etching the ILD layer using the patterned photoresist layer as a hard mask to simultaneously form the first plurality of through-hole openings and the first plurality of shallow-etched regions in the ILD layer.

15. The method of claim 14 , wherein each of the plurality of light-shielding structures comprises a first surface and a second surface, wherein the first surface is coplanar with the ILD layer, and wherein the second surface comprises wrinkles.

16. The method of claim 14 , wherein the light-shielding structure in each of the plurality of pixels comprises tungsten (W) metal and electrically grounded through at least one grounding contact.

17. The method of claim 14 , wherein a first thickness of the light-shielding structure is at least 150 nanometers, and wherein a second thickness of the ILD layer is at least 330 nanometers.

18. The method of claim 14 , wherein the charge-storage region comprises at least one of the following: at least one transfer gate and a charge-storage node.

19. The method of claim 14 , wherein the at least one via contact is configured to provide electrical contacts to the charge-storage region and is electrically isolated from the light-shielding structure, wherein the at least one via contact comprises W metal.

20. The method of claim 14 , further comprising:

forming a vertical shift register (VSR), wherein the VSR is coupled with the pixel array to perform at least one of the following functions, receiving a row address of the pixel array and driving control lines of the pixel array;

forming a horizontal shift register (HSR), wherein the HSR is coupled with the pixel array to perform reading output signals from the pixel array;

providing a timing generator coupled to the pixel array, the VSR and the HSR so as to generate a clock signal for synchronization purposes; and

providing a voltage regulator coupled to the pixel array, the VSR and the HSR so as to provide voltage control and maintain voltage levels.