IP Library › Granted Patent US 12,100,747
Granted Patent B2
US 12,100,747 · App. 17/286,530 · Granted Sep 24, 2024

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Yukinori Shima (Gunma, JP); Masataka Nakada (Tochigi, JP); Takumi Shigenobu (Tochigi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/4908H01L29/42384H01L29/66969G02F1/13685H01L2029/42388H01L29/7869H10K59/12
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Quick Facts
Patent No.
US 12,100,747
App. No.
17/286,530
Granted
Sep 24, 2024
Kind
B2
Abstract

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device capable of high-voltage driving is provided. A semiconductor device in which a large amount of current can flow is provided. The semiconductor device has a structure including a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, a conductive layer, and an insulating region. The metal oxide layer is positioned between the first insulating layer and the conductive layer. The insulating region is adjacent to the metal oxide layer and is positioned between the first insulating layer and the conductive layer. The semiconductor layer includes a first region in contact with the first insulating layer and overlapping with the metal oxide layer and the conductive layer with the first insulating layer therebetween, a second region in contact with the first insulating layer and overlapping with the insulating region and the conductive layer with the first insulating layer therebetween, a third region in contact with the first insulating layer, and a fourth region in contact with the second insulating layer. The insulating region shows a different permittivity from the first insulating layer.

Claims (51)

1. A semiconductor device comprising:

a semiconductor layer;

a first insulating layer;

a second insulating layer;

a metal oxide layer;

a conductive layer; and

an insulating region,

wherein the metal oxide layer is positioned between the first insulating layer and the conductive layer,

wherein the insulating region is adjacent to the metal oxide layer and is positioned between the first insulating layer and the conductive layer,

wherein the semiconductor layer comprises a first region, a second region, a third region, and a fourth region,

wherein the first region is in contact with the first insulating layer and overlaps with the metal oxide layer and the conductive layer with the first insulating layer therebetween,

wherein the second region is in contact with the first insulating layer and overlaps with the insulating region and the conductive layer with the first insulating layer therebetween,

wherein the third region is in contact with the first insulating layer,

wherein the fourth region is in contact with the second insulating layer,

wherein the insulating region has a different permittivity from the first insulating layer,

wherein the insulating region has a different permittivity from the second insulating layer, and

wherein the first region has the lowest hydrogen concentration and the fourth region has the highest hydrogen concentration among the first region, the second region, the third region, and the fourth region.

2. The semiconductor device according to claim 1 ,

wherein, in a plan view,

an end portion of the metal oxide layer is positioned inward from an end portion of the conductive layer, and

wherein the end portion of the conductive layer is positioned inward from an end portion of the first insulating layer.

3. The semiconductor device according to claim 2 ,

wherein the first insulating layer, the metal oxide layer and the conductive layer are processed using the same resist mask.

4. The semiconductor device according to claim 1 ,

wherein the insulating region comprises a space, and

wherein the space is filled with a gas.

5. The semiconductor device according to claim 1 ,

wherein the first region has the lowest carrier concentration and the fourth region has the highest carrier concentration among the first region, the second region, the third region, and the fourth region.

6. A semiconductor device comprising:

a semiconductor layer;

a first insulating layer;

a second insulating layer;

a metal oxide layer;

a conductive layer;

an insulating region; and

a third insulating layer and a fourth insulating layer,

wherein the metal oxide layer is positioned between the first insulating layer and the conductive layer,

wherein the insulating region is adjacent to the metal oxide layer and is positioned between the first insulating layer and the conductive layer,

wherein the semiconductor layer comprises a first region, a second region, a third region, and a fourth region,

wherein the first region is in contact with the first insulating layer and overlaps with the metal oxide layer and the conductive layer with the first insulating layer therebetween,

wherein the second region is in contact with the first insulating layer and overlaps with the insulating region and the conductive layer with the first insulating layer therebetween,

wherein the third region is in contact with the first insulating layer,

wherein the fourth region is in contact with the second insulating layer,

wherein the insulating region has a different permittivity from the first insulating layer, and

wherein the insulating region has a different permittivity from the second insulating layer,

wherein the third insulating layer comprises a region overlapping with the first insulating layer with the semiconductor layer therebetween,

wherein the fourth insulating layer comprises a region overlapping with the semiconductor layer with the third insulating layer therebetween,

wherein the third insulating layer comprises an oxide, and

wherein the fourth insulating layer comprises a nitride.

7. The semiconductor device according to claim 6 ,

wherein the fourth insulating layer comprises a portion in contact with the second insulating layer in a region not overlapping with the semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2021
From: YAMAZAKI, SHUNPEI; SHIMA, YUKINORI; NAKADA, MASATAKA; SHIGENOBU, TAKUMI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 055956/0384 →
Priority Claims (1)
JP 2018-207250 · Nov 2, 2018 · national
Continuity (1)
Related Publication 20210384314A1 · Dec 9, 2021
Cited By (2)
US 12,356,640 US 12,414,313