NMOS and PMOS transistor gates with hafnium oxide layers and lanthanum oxide layers

1. A method comprising:

forming a silicon oxide layer comprising a first portion and a second portion over a first semiconductor region and a second semiconductor region, respectively;

depositing a first high-k dielectric layer comprising a first portion and a second portion over the first portion and the second portion, respectively, of the silicon oxide layer;

depositing a plurality of dielectric layers comprising a first portion and a second portion over the first portion and the second portion, respectively, of the first high-k dielectric layer;

removing the second portion of the plurality of dielectric layers to reveal the second portion of the first high-k dielectric layer;

forming a second high-k dielectric layer over the second portion of the first high-k dielectric layer; and

depositing a metal-containing layer comprising a first portion and a second portion over the first portion of the first high-k dielectric layer and the second high-k dielectric layer, respectively.

2. The method of claim 1 , wherein the depositing the plurality of dielectric layers comprises depositing a lanthanum oxide layer.

3. The method of claim 2 , wherein the depositing the plurality of dielectric layers further comprises depositing a lanthanum silicon oxide layer over the lanthanum oxide layer is deposited.

4. The method of claim 1 , wherein the depositing the first high-k dielectric layer comprises depositing a hafnium silicon oxide layer.

5. The method of claim 4 , wherein the depositing the plurality of dielectric layers further comprises depositing a hafnium oxide layer, wherein the hafnium silicon oxide layer is between the hafnium oxide layer and the silicon oxide layer.

6. The method of claim 4 , wherein the hafnium silicon oxide layer has a hafnium atomic percentage lower than about 10 percent.

7. The method of claim 1 , wherein at a time before the first high-k dielectric layer is deposited, the silicon oxide layer is free from hafnium.

8. The method of claim 1 , wherein the depositing the metal-containing layer comprises depositing a work-function layer directly over both of the first semiconductor region and the second semiconductor region.

9. The method of claim 1 , wherein the depositing the metal-containing layer comprises depositing a titanium silicon nitride layer directly over both of the first semiconductor region and the second semiconductor region.

10. The method of claim 1 , wherein the forming the second high-k dielectric layer comprises:

depositing the second high-k dielectric layer directly over both of the first semiconductor region and the second semiconductor region; and

removing the second high-k dielectric layer from a region directly over the first semiconductor region.

11. A method comprising:

forming a silicon oxide layer comprising a first portion and a second portion over a first semiconductor region and a second semiconductor region, respectively;

depositing a hafnium silicon oxide layer comprising a first portion and a second portion over the first portion and the second portion, respectively, of the silicon oxide layer;

depositing a lanthanum oxide layer comprising a first portion and a second portion over the first portion and the second portion, respectively, of the hafnium silicon oxide layer;

removing the second portion of the lanthanum oxide layer, wherein the first portion of the hafnium silicon oxide layer remains after the removing; and

forming a high-k dielectric layer over the second portion of the hafnium silicon oxide layer.

12. The method of claim 11 further comprising:

depositing a first work function layer over the first portion of the lanthanum oxide layer; and

depositing a second work function layer over the high-k dielectric layer, respectively.

13. The method of claim 11 , wherein the high-k dielectric layer is in physical contact with the second portion of the hafnium silicon oxide layer.

14. The method of claim 11 , wherein the forming the high-k dielectric layer comprises:

depositing a hafnium oxide layer directly over both of the first semiconductor region and the second semiconductor region; and

removing the hafnium oxide layer from a region directly over the first semiconductor region.

15. The method of claim 11 further comprising:

forming n-type source/drain regions extending into the first semiconductor region; and

forming p-type source/drain regions extending into the second semiconductor region.

16. The method of claim 11 further comprising depositing a titanium silicon nitride layer comprising:

a first portion over the first portion of the lanthanum oxide layer; and

a second portion over and in contact with the high-k dielectric layer.

17. The method of claim 11 further comprising:

depositing a lanthanum silicon oxide layer comprising a first portion and a second portion over the first portion and the second portion, respectively, of the lanthanum oxide layer; and

removing the second portion of the lanthanum silicon oxide layer.

18. A method comprising:

forming a gate stack of a transistor, the forming the gate stack comprising:

forming a silicon oxide layer on a semiconductor region;

depositing a hafnium silicon oxide layer over the silicon oxide layer;

depositing a lanthanum oxide layer over the hafnium silicon oxide layer;

removing the lanthanum oxide layer to reveal the hafnium silicon oxide layer;

after the lanthanum oxide layer is removed, depositing a high-k dielectric layer over and contacting the hafnium silicon oxide layer; and

forming a source/drain region on a side of the gate stack.

19. The method of claim 18 further comprising:

depositing a hafnium oxide layer over the hafnium silicon oxide layer.

20. The method of claim 18 , wherein the high-k dielectric layer further comprises hafnium oxide.