Methods and apparatus to implement current limit test mode
Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.
1. A circuit comprising:
a first transistor having first and second current terminals and a first control terminal, wherein the first current terminal is coupled to an input voltage terminal, and a body of the first transistor is coupled to a ground terminal;
a second transistor having third and fourth current terminals and a second control terminal, wherein the second control terminal is coupled to the second current terminal and the fourth current terminal, and the third current terminal is coupled to the input voltage terminal;
a charge pump circuit having a charge pump input and a charge pump output, wherein the charge pump input is coupled to the first and third current terminals; and
a third transistor having a fifth and sixth current terminals and a third control terminal, wherein the fifth current terminal is coupled to the first control terminal; and
a fourth transistor having seventh and eighth current terminals and a fourth control terminal, wherein the seventh current terminal is coupled to the sixth current terminal, the fourth control terminal is coupled to the third control terminal, and the eighth current terminal is coupled to the charge pump output.
2. The circuit of claim 1 , further comprising:
a fifth transistor having ninth and tenth current terminals and a fifth control terminal, wherein the ninth current terminal is coupled to the fourth control terminal, and the fifth control terminal is coupled to the input voltage terminal; and
a sixth transistor having eleventh and twelfth current terminals and a sixth control terminal, wherein the eleventh current terminal is coupled to the tenth current terminal, and the twelfth current terminal is coupled to the eighth current terminal.
3. The circuit of claim 2 , further comprising:
a seventh transistor having thirteenth and fourteenth current terminals and a seventh control terminal, wherein the thirteenth current terminal is coupled to the tenth current terminal, the fourteenth current terminal is coupled to the ground terminal, and the seventh control terminal is coupled to the ground terminal.
4. The circuit of claim 3 , wherein a body of the seventh transistor is coupled to the ground terminal.
5. The circuit of claim 2 , wherein the second, third, fourth, fifth and sixth transistors each have a respective body diode coupled between respective current terminals of the second, third, fourth, fifth and sixth transistors.
6. The circuit of claim 2 , further comprising a high-side drive (HSD) transistor having a HSD gate, a HSD source, and a HSD drain, wherein the HSD gate is coupled to the eighth current terminal.
7. The circuit of claim 6 , wherein the HSD transistor is a first HSD transistor, the HSD gate is a first HSD gate, the HSD drain is a first HSD drain, the HSD source is a first HSD source, and the circuit further comprises a second HSD transistor having a second HSD gate, a second HSD source, and a second HSD drain, wherein the second HSD gate is coupled to the first control terminal.
8. The circuit of claim 7 , wherein the second HSD source is coupled to the first HSD source, and the second HSD drain is coupled to the second HSD drain.
9. The circuit of claim 8 , further comprising an eighth transistor coupled between the first HSD gate and the ground terminal.
10. The circuit of claim 9 , wherein a body of the eighth transistor is coupled to the ground terminal.
11. The circuit of claim 7 , further comprising a low-side drive (LSD) transistor coupled between the first HSD source and the ground terminal, and having a LSD gate, wherein the LSD gate is coupled to a gate driver circuit.
12. The circuit of claim 1 , wherein the first transistor is an n-channel field effect transistor (NFET) and the second, third and fourth transistors are p-channel field effect transistors (PFETs).
13. The circuit of claim 1 , further comprising a controller coupled to the charge pump circuit, wherein the controller is configurable to enable or disable the charge pump circuit.
14. The circuit of claim 13 , wherein the controller includes a signal generator configured to provide a signal to the charge pump circuit.
15. The circuit of claim 14 , wherein the signal is a pulse width modulated (PWM) signal.