Scan frame based test access mechanisms
Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.
1. An integrated circuit comprising:
a serial data input lead;
a scan frame input register including:
a compressed stimulus section coupled to the serial data input lead;
a command section coupled to the compressed stimulus section; and
a frame marker section coupled to the command section;
a decompressor circuit including an input coupled to the compressed stimulus section, wherein the decompressor circuit further includes an output;
core scan paths including an input coupled to the output of the decompressor circuit, wherein the core scan paths further include an output; and
a compressor circuit including an input coupled to the output of the core scan paths.
2. The integrated circuit of claim 1 ,
wherein the compressed stimulus section is a first compressed stimulus section,
wherein the command section is a first command section, and
wherein the integrated circuit further comprises a scan frame update register including:
a second compressed stimulus section coupled to the first compressed stimulus section and coupled to the input of the decompressor circuit; and
a second command section coupled to the first command section.
3. The integrated circuit of claim 2 , further comprising a controller including:
a first input coupled to the frame marker section; and
a second input coupled to the second command section.
4. The integrated circuit of claim 3 , wherein the controller comprises an output coupled to the first compressed stimulus section, the second compressed stimulus section, the first command section, the second command section, the frame marker section, the compressor circuit, and the core scan paths.
5. The integrated circuit of claim 3 , wherein the controller is configured to:
cause a first scan frame to be input from the serial data input lead to the scan frame input register; and
simultaneously with causing the first scan frame to be input, cause the core scan paths to perform a test operation on a second scan frame based on the command section.
6. The integrated circuit of claim 1 , wherein the scan frame input register comprises a mask section coupled to the compressor circuit.
7. The integrated circuit of claim 1 ,
wherein the decompressor circuit is a first decompressor circuit,
wherein the scan frame input register comprises a compressed mask section, and
wherein the integrated circuit further comprises a second decompressor circuit including:
an input coupled to the compressed mask section; and
an output coupled to the compressor circuit.
8. The integrated circuit of claim 7 ,
wherein the compressor circuit comprises a comparator including a first input coupled to the output of the core scan paths,
wherein the scan frame input register comprises a compressed response section,
wherein the integrated circuit further comprises a third decompressor circuit including an input coupled to the compressed response section,
wherein the comparator further includes a second input coupled to the second decompressor circuit, and
wherein the comparator further includes a third input coupled to the third decompressor circuit.
9. The integrated circuit of claim 1 ,
wherein the compressor circuit comprises a comparator including a first input coupled to the output of the core scan paths,
wherein the scan frame input register comprises a response section, and
wherein the comparator further includes a second input coupled to the response section.
10. The integrated circuit of claim 1 ,
wherein the decompressor circuit is a first decompressor circuit,
wherein the compressor circuit comprises a comparator including a first input coupled to the output of the core scan paths,
wherein the scan frame input register comprises a compressed response section,
wherein the integrated circuit further comprises a second decompressor circuit including an input coupled to the compressed response section, and
wherein the comparator further includes a second input coupled to the second decompressor circuit.
11. The integrated circuit of claim 1 , further comprising:
a serial data output lead; and
a multiplexer including:
an input coupled to the compressor circuit; and
an output coupled to serial data output lead.
12. An integrated circuit comprising:
a serial data input lead;
a scan frame input register coupled to the serial data input lead;
core scan paths including an input coupled to the scan frame input register; and
a controller coupled to the scan frame input register and coupled to the core scan paths,
wherein the controller is configured to:
cause a first scan frame to be input from the serial data input lead to the scan frame input register; and
simultaneously with causing the first scan frame to be input, cause the core scan paths to perform a test operation on a second scan frame.
13. The integrated circuit of claim 12 , further comprising a compressor circuit including a first input coupled to the core scan paths,
wherein the scan frame input register comprises a mask section, and
wherein the compressor circuit further includes a second input coupled to the mask section.
14. The integrated circuit of claim 12 , further comprising a comparator including a first input coupled to the core scan paths,
wherein the scan frame input register comprises a response section, and
wherein the comparator further includes a second input coupled to the response section.